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1. 发明申请

US20120089861A1 INTER-PROCESSOR FAILURE DETECTION AND RECOVERY 有权
标题翻译：处理器故障检测和恢复
公开(公告)号：US20120089861A1
公开(公告)日：2012-04-12
申请号：US12902501
申请日：2010-10-12
申请人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F11/07 , G06F11/00
CPC分类号： G06F11/0757 , G06F11/0724
摘要： An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
摘要翻译：公开了一种在多处理器环境中检测处理器故障的方法。该方法可以包括使系统中的每个CPU负责监视系统中的另一个CPU。 CPUn读取CPUn + 1创建的时间戳+1，CPUn正在从共享内存位置进行监控。 CPUn读取自己的时间戳，并比较两个时间戳来计算增量值。如果增量值高于阈值，CPUn确定CPUn + 1失败，并启动系统中CPU的错误处理。一个CPU可能被指定为主CPU，并负责开始错误处理过程。在这种实施例中，CPUn可以通过通知主CPU CPUn + 1失败来启动错误处理。如果CPUn + 1是主CPU，CPUn可能会采取额外的步骤来启动错误处理，并可能会向所有CPU广播非关键中断，从而触发错误处理。

2. 发明授权

US08850262B2 Inter-processor failure detection and recovery 有权
标题翻译：处理器间故障检测和恢复
公开(公告)号：US08850262B2
公开(公告)日：2014-09-30
申请号：US12902501
申请日：2010-10-12
申请人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Timothy J. Van Patten
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0757 , G06F11/0724
摘要： An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
摘要翻译：公开了一种在多处理器环境中检测处理器故障的方法。该方法可以包括使系统中的每个CPU负责监视系统中的另一个CPU。 CPUn读取CPUn + 1创建的时间戳+1，CPUn正在从共享内存位置进行监控。 CPUn读取自己的时间戳，并比较两个时间戳来计算增量值。如果增量值高于阈值，CPUn确定CPUn + 1失败，并启动系统中CPU的错误处理。一个CPU可能被指定为主CPU，并负责开始错误处理过程。在这种实施例中，CPUn可以通过通知主CPU CPUn + 1失败来启动错误处理。如果CPUn + 1是主CPU，CPUn可能会采取额外的步骤来启动错误处理，并可能会向所有CPU广播非关键中断，从而触发错误处理。

3. 发明授权

US09075720B2 Locking a cache line for write operations on a bus 有权
标题翻译：在总线上锁定缓存行以进行写操作
公开(公告)号：US09075720B2
公开(公告)日：2015-07-07
申请号：US12897555
申请日：2010-10-04
申请人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
发明人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0879 , G06F12/0802 , G06F12/0804 , G06F12/0833 , G06F12/0891 , G06F12/1009 , G06F12/127 , G06F12/1475 , G06F2212/1052 , G06F2212/303 , G06F2212/604 , G06F2212/62 , G06F2212/657
摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
摘要翻译：提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。在目标地址的缓存中分配高速缓存行。为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。数据被写入缓存行。响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。

4. 发明申请

US20120084514A1 LOCKING A CACHE LINE FOR WRITE OPERATIONS ON A BUS 有权
标题翻译：锁定用于在总线上进行写操作的高速缓存线
公开(公告)号：US20120084514A1
公开(公告)日：2012-04-05
申请号：US12897555
申请日：2010-10-04
申请人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
发明人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
IPC分类号： G06F12/08 , G06F13/24 , G06F12/00
CPC分类号： G06F12/0879 , G06F12/0802 , G06F12/0804 , G06F12/0833 , G06F12/0891 , G06F12/1009 , G06F12/127 , G06F12/1475 , G06F2212/1052 , G06F2212/303 , G06F2212/604 , G06F2212/62 , G06F2212/657
摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
摘要翻译：提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。在目标地址的缓存中分配高速缓存行。为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。数据被写入缓存行。响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。

5. 发明授权

US08904058B2 Selecting direct memory access engines in an adaptor input/output (I/O) requests received at the adaptor 有权
标题翻译：在适配器上接收的适配器输入/输出（I / O）请求中选择直接内存访问引擎
公开(公告)号：US08904058B2
公开(公告)日：2014-12-02
申请号：US13118093
申请日：2011-05-27
申请人： Charles S. Cardinell , Roger G. Hathorn , Matthew J. Kalos , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Matthew J. Kalos , Timothy J. Van Patten
IPC分类号： G06F13/28 , G06F13/00 , G06F9/50
CPC分类号： G06F13/28 , G06F9/5011 , G06F9/505
摘要： Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.
摘要翻译：提供了一种用于在适配器中选择直接存储器访问（DMA）引擎以用于处理在适配器处接收的输入/输出请求的计算机程序产品，系统和方法。确定将多个处理器分配给DMA引擎，其中分配每个处理器以使用DMA引擎之一。通过确定分配给处理器的处理I / O请求相关工作的DMA引擎并访问确定的DMA引擎来执行与I / O相关的工作来处理针对存储器的接收的I / O请求的I / O请求相关工作。

6. 发明申请

US20120303842A1 SELECTING DIRECT MEMORY ACCESS ENGINES IN AN ADAPTOR FOR PROCESSING INPUT/OUTPUT (I/O) REQUESTS RECEIVED AT THE ADAPTOR 有权
标题翻译：在适配器中选择直接存储器访问引擎，用于处理在适配器中接收的输入/输出（I / O）请求
公开(公告)号：US20120303842A1
公开(公告)日：2012-11-29
申请号：US13118093
申请日：2011-05-27
申请人： Charles S. Cardinell , Roger G. Hathorn , Matthew J. Kalos , Timothy J. Van Patten
发明人： Charles S. Cardinell , Roger G. Hathorn , Matthew J. Kalos , Timothy J. Van Patten
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F9/5011 , G06F9/505
摘要： Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.
摘要翻译：提供了一种用于在适配器中选择直接存储器访问（DMA）引擎以用于处理在适配器处接收的输入/输出请求的计算机程序产品，系统和方法。确定将多个处理器分配给DMA引擎，其中分配每个处理器以使用DMA引擎之一。通过确定分配给处理器的处理I / O请求相关工作的DMA引擎并访问确定的DMA引擎来执行与I / O相关的工作来处理针对存储器的接收的I / O请求的I / O请求相关工作。

7. 发明授权

US08769173B2 Systems and methods for detecting supported small form-factor pluggable (SFP) devices 有权
标题翻译：用于检测支持的小型可插拔（SFP）设备的系统和方法
公开(公告)号：US08769173B2
公开(公告)日：2014-07-01
申请号：US12904721
申请日：2010-10-14
申请人： Charles S. Cardinell , Roger G. Hathorn , Steven E. Klein , Ashwani Kumar , Daniel W. Sherman
发明人： Charles S. Cardinell , Roger G. Hathorn , Steven E. Klein , Ashwani Kumar , Daniel W. Sherman
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/00 , G06F11/3034 , G06F11/3051 , G06F2213/0008
摘要： Systems and methods for detecting supported small form-factor pluggable (SFP) devices in an adapter are provided. One system includes multiple ports, each port configured to be coupled to a SFP device, a tracking device configured to store data representing a list of supported SFP devices for the adapter, and a processor coupled to each of the plurality of ports and the tracking device. The processor is configured to scan each port at start-up, determine if any of the ports is coupled to a non-supported SFP device, and disable any ports that are coupled to a non-supported SFP device. One method includes scanning each port at start-up, determining if any of the ports is coupled to a non-supported SFP device, and disabling any ports that are coupled to a non-supported SFP device. Also provided are computer storage mediums including computer code for performing the above method.
摘要翻译：提供了用于检测适配器中支持的小型可插拔（SFP）设备的系统和方法。一个系统包括多个端口，每个端口被配置为耦合到SFP设备，跟踪设备被配置为存储表示用于适配器的支持的SFP设备的列表的数据，以及耦合到多个端口中的每个端口的跟踪设备。处理器配置为在启动时扫描每个端口，确定是否有任何端口耦合到不支持的SFP设备，并禁用耦合到不支持SFP设备的任何端口。一种方法包括在启动时扫描每个端口，确定是否有任何端口耦合到不支持的SFP设备，以及禁用耦合到不支持SFP设备的任何端口。还提供了包括用于执行上述方法的计算机代码的计算机存储介质。

8. 发明授权

US09065760B2 Priority data transmission using Fibre Channel over Ethernet 有权
标题翻译：使用以太网光纤通道进行优先级数据传输
公开(公告)号：US09065760B2
公开(公告)日：2015-06-23
申请号：US12854048
申请日：2010-08-10
申请人： Louie A. Dickens , Roger G. Hathorn , Richard Hutzler , William M Smith, Jr. , Michael E. Starling , Daniel J. Winarski
发明人： Louie A. Dickens , Roger G. Hathorn , Richard Hutzler , William M Smith, Jr. , Michael E. Starling , Daniel J. Winarski
IPC分类号： H04L12/851 , H04L12/801
CPC分类号： H04L47/24 , H04L47/12 , H04L47/2441
摘要： An apparatus, system, and method are disclosed for handling data being communicated over lossless Ethernet that is sensitive to delays. Fiber Channel over Ethernet (FCoE) is one example of an environment where data may be subject to unacceptable delays. The method involves designating certain data as low latency data that is sensitive to delays in transmission. The low latency data is then transmitted in such a manner that the receiving devices are aware that they are receiving low latency data. If a delay in the transmission of low latency is detected, commands are issued that pause or slow standard data in order to free up bandwidth for the low latency data. The commands may be, for example, backward congestion notifications and priority flow control. Low latency data is exempted from backward congestion notifications and priority flow control. Priority 7 priority group 15 may be reserved exclusively for low latency data.
摘要翻译：公开了一种用于处理通过对延迟敏感的无损以太网传送的数据的装置，系统和方法。以太网光纤通道（FCoE）是数据可能遭受不可接受的延迟的一个例子。该方法包括将某些数据指定为对传输延迟敏感的低延迟数据。然后以这样的方式传送低延迟数据，使得接收设备知道它们正在接收低延迟数据。如果检测到低延迟传输的延迟，则发出暂停或减慢标准数据的命令，以释放低延迟数据的带宽。这些命令可以是例如反向拥塞通知和优先级流控制。低延迟数据免于后向拥塞通知和优先流控制。优先级7优先级组15可以专门用于低延迟数据。

9. 发明申请

US20130272313A1 UPDATING ZONE INFORMATION IN A DISTRIBUTED SWITCH OF DATA FORWARDERS 有权
公开(公告)号：US20130272313A1
公开(公告)日：2013-10-17
申请号：US13449164
申请日：2012-04-17
申请人： Roger G. Hathorn , Sriharsha Jayanarayana , Henry J. May , Stefan Roscher , Bharath B. Somayaji , Sudheer R. Yelanduru
发明人： Roger G. Hathorn , Sriharsha Jayanarayana , Henry J. May , Stefan Roscher , Bharath B. Somayaji , Sudheer R. Yelanduru
IPC分类号： H04L12/56
CPC分类号： H04L45/02 , H04L45/021
摘要： Provided are a computer program product, system, and method for updating zone information in a distributed switch of data forwarders. For each data forwarder, a sequence number is maintained for zone distribution messages sent to the data forwarder. A change to the ports in the network is detected comprising at least one of an allocation or deallocation of at least one port in the network. The sequence number for each data forwarder is incremented in response to detecting the change. For each data forwarder, a zone distribution message is generated indicating the at least one port allocated and/or deallocated, port information indicating each port in the network that may communicate with each other port, and the sequence number for the data forwarder. The generated zone distribution message is transmitted for each data forwarder to the data forwarder for which the zone distribution message was added.

10. 发明申请

US20120159003A1 SYSTEMS AND METHODS FOR AVOIDING HOST LEVEL BUSY AND RETRY LATENCIES 失效
标题翻译：避免主机级和重新启动的系统和方法
公开(公告)号：US20120159003A1
公开(公告)日：2012-06-21
申请号：US12972313
申请日：2010-12-17
申请人： Matthew R. Craig , Clint A. Hardy , Roger G. Hathorn , Bret W. Holley
发明人： Matthew R. Craig , Clint A. Hardy , Roger G. Hathorn , Bret W. Holley
IPC分类号： G06F3/00
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0689
摘要： In one embodiment, a system includes logic adapted for receiving a command from a first system, logic adapted for determining which resources are required to process the command, logic adapted for checking for the required resources before receiving data associated with the command, logic adapted for receiving the data from the first system, logic adapted for checking for the required resources after receiving the data when the checking for the required resources before receiving data indicated that the required resources were not available before receiving the data, logic adapted for sending a status to the first system if the required resources are not available after receiving the data, and logic adapted for processing the command if the required resources are available either before receiving the data or after receiving the data. In more embodiments, a method and computer program product for processing a command are also presented.
摘要翻译：在一个实施例中，系统包括适于从第一系统接收命令的逻辑，适于确定需要哪些资源来处理命令的逻辑，适于在接收与命令相关联的数据之前检查所需资源的逻辑，从第一系统接收数据，适于在接收数据之前检查所需资源的接收数据之后检查所需资源的逻辑指示在接收数据之前所需资源不可用，适于发送状态的逻辑如果在接收到数据之后所需资源不可用的第一系统，以及如果所需资源在接收数据之前或在接收到数据之后可用的逻辑，则适于处理该命令。在更多实施例中，还呈现了用于处理命令的方法和计算机程序产品。

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