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    • 1. 发明申请
    • TRANSISTOR AND ITS METHOD OF MANUFACTURE
    • 晶体管及其制造方法
    • WO2018055371A1
    • 2018-03-29
    • PCT/GB2017/052806
    • 2017-09-20
    • PRAGMATIC PRINTING LTD.
    • PRICE, RichardGREEN, NathanielDAVIES, NeilTHORNDYKE, AdrianALKHALIL, Feras
    • H01L29/423H01L29/49H01L29/786
    • A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material. The transistor further comprises a layer of a second dielectric material having a second dielectric constant, the second dielectric constant being lower than the first dielectric constant, the layer of second dielectric material being arranged between at least part of the first overlapping portion and the first terminal, whereby at least part of the first overlapping portion of the gate terminal is separated from the first terminal by the layer of first dielectric material and the layer of second dielectric material.
    • 公开了一种晶体管,包括:半导体材料层,其包括第一部分,第二部分和将所述第一部分连接至所述第二部分的第三部分,并且在所述第一部分与所述第二部分之间提供半导电沟道, 和第二部分; 导电的第一端子,覆盖所述半导体材料层的所述第一部分并与所述第一部分电接触; 导电的第二端子,覆盖并与所述半导体材料层的所述第二部分电接触; 导电栅极端子,包括覆盖所述第一端子的至少一部分的第一重叠部分和覆盖所述半导体材料层的第三部分的沟道部分; 以及布置在第一重叠部分和第一端子之间以及栅极端子的沟道部分和半导体材料层的第三部分之间的具有第一介电常数的第一介电材料层。 所述晶体管还包括具有第二介电常数的第二介电材料层,所述第二介电常数低于所述第一介电常数,所述第二介电材料层布置在所述第一重叠部分的至少一部分与所述第一端子 由此,栅极端子的第一重叠部分的至少一部分通过第一介电材料层和第二介电材料层与第一端子分离。