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    • 4. 发明授权
    • Image stabilizing control method offering a short waiting time for
operation recovery and image forming apparatus incorporating said
control method
    • 图像稳定控制方法提供了操作恢复的等待时间短并且包含所述控制方法的图像形成装置
    • US5966557A
    • 1999-10-12
    • US199807
    • 1998-11-25
    • Kenichi Wada
    • Kenichi Wada
    • G03G15/00
    • G03G15/5012G03G15/5037G03G15/5041G03G2215/00042G03G2215/00054G03G2215/00084
    • The differences in the detected values of temperature and humidity between the time at which the suspension of operation begins and the time at which operation is restored are sought, and the differences are compared with their respective prescribed thresholds. If the difference in temperature is less than the threshold and the difference in relative humidity is less than the threshold, as an example, it is determined that the environmental change during the period of suspension of operation is less than the threshold, and the copying machine is made ready immediately without performing image stabilizing control. On the other hand, where the difference in temperature equals or exceeds the threshold, or where the difference in relative humidity equals or exceeds the threshold, it is determined that the environmental change during the period of suspension of operation equals or exceeds the threshold, whereupon image stabilizing control is executed and the image forming operation parameters are set. The copying machine is then made ready.
    • 寻求在开始暂停操作的时间和恢复操作的时间之间的温度和湿度的检测值的差异,并将差异与它们各自的规定阈值进行比较。 如果温度差小于阈值并且相对湿度差小于阈值,则作为示例,确定在操作中止期间的环境变化小于阈值,并且复印机 立即就绪,不进行图像稳定控制。 另一方面,当温度差等于或超过阈值时,或相对湿度差等于或超过阈值时,确定在操作暂停期间的环境变化等于或超过阈值,于是, 执行图像稳定控制,并且设置图像形成操作参数。 然后复印机准备就绪。
    • 5. 发明授权
    • Multiprocessor system having subsystems which are loosely coupled
through a random access storage and which each include a tightly
coupled multiprocessor
    • 具有通过随机存取存储松散耦合的子系统的多处理器系统,每个子系统包括紧密耦合的多处理器
    • US5201040A
    • 1993-04-06
    • US209073
    • 1988-06-20
    • Kenichi WadaAkira Yamaoka
    • Kenichi WadaAkira Yamaoka
    • G06F15/17
    • G06F15/17
    • A data processing system which has a plurality of sets of sub-systems, with each set including: a plurality of processors; a main storage; and a controller for controlling the transfer between at least each of the processors and the main storage. A shared storage apparatus is shared between the sub-systems to store exclusive control information, information on the processor-to-processor communications and an instruction to be transferred between the main storages and the shared storage apparatus when the information is accessed by each sub-system. The instruction designates a main storage address, a transfer data length and specified information on accessing the location of the shared storage apparatus and is decoded by the processors to that the main storage address is transferred to the main storage, whereas the specified information such as a data identifier and a relative address is transferred to the shared storage apparatus.
    • 一种具有多组子系统的数据处理系统,每组包括:多个处理器; 主要存储; 以及用于控制至少每个处理器和主存储器之间的传送的控制器。 在每个子系统访问信息时,在子系统之间共享共享存储装置以存储专用控制信息,关于处理器到处理器通信的信息和要在主存储器和共享存储装置之间传送的指令, 系统。 该指令指定主存储地址,传输数据长度和关于访问共享存储设备的位置的指定信息,并且被处理器解码为主存储地址被传送到主存储器,而指定的信息例如 数据标识符和相对地址被传送到共享存储装置。
    • 7. 发明授权
    • Information processing system with instruction address saving function
corresponding to priority levels of interruption information
    • 具有指令地址保存功能的信息处理系统对应于中断信息的优先级
    • US5032980A
    • 1991-07-16
    • US241375
    • 1988-09-07
    • Seiichi OzakiKenichi WadaShigeki Morimoto
    • Seiichi OzakiKenichi WadaShigeki Morimoto
    • G06F9/38G06F9/46G06F9/48
    • G06F9/4812G06F9/3861G06F9/462
    • A level machine information system is provided with an instruction register for storing an address of an instruction read out from an instruction memory, an instruction decoder for producing control signals complying with the instruction read out, a calculator for producing a new address of an instruction to be executed next on the basis of the address outputted from the instruction register, an instruction length code supplied from the decoder as the control signals, a plurality of first registers for saying the address outputted from the instruction register, a plurality of second registers for saving the new address, a controller and a selector for supplying the instruction register with the new address, the saved new address and fixed addresses each indicating the head of interruption programs in the instruction memory. The first and second registers correspond to all but the highest interruption priority level. Upon an acknowledged interruption request, the controller controls the first and second registers and selector to save the new address of the calculator and the old address of the instruction register in one of the first and second registers corresponding to the priority levels of an interrupted process, respectively. One of the fixed addresses corresponding to a process to be executed for the interruption request is transferred in the instruction register. If necessary, the contents of the first and second registers are referenced by the process to detect the reasons for the interruption.
    • 级别机器信息系统设置有用于存储从指令存储器读出的指令的地址的指令寄存器,用于产生符合读出指令的控制信号的指令解码器,用于产生指令的新地址的计算器 基于从指令寄存器输出的地址,从解码器提供的作为控制信号的指令长度代码,用于表示从指令寄存器输出的地址的多个第一寄存器,多个用于保存的第二寄存器 新地址,用于向指令寄存器提供新地址的控制器和选择器,保存的新地址和固定地址,每个指示指令存储器中的中断程序的开头。 第一和第二寄存器对应于除最高中断优先级之外的所有寄存器。 在确认的中断请求之后,控制器控制第一和第二寄存器和选择器以将计算器的新地址和指令寄存器的旧地址保存在与中断处理的优先级相对应的第一和第二寄存器之一中, 分别。 与中断请求执行的处理相对应的固定地址之一被传送到指令寄存器中。 如有必要,第一和第二寄存器的内容由进程引用,以检测中断的原因。
    • 8. 发明授权
    • Instruction processor for processing branch instruction at high speed
    • 高速处理分支指令的指令处理器
    • US4954947A
    • 1990-09-04
    • US336741
    • 1989-03-21
    • Kazunori KuriyamaKenichi WadaAkira Yamaoka
    • Kazunori KuriyamaKenichi WadaAkira Yamaoka
    • G06F9/38
    • G06F9/3824
    • An instruction processor effecting operations for register operands and for processing branch instructions to perform address calculations for branch destination instructions, comprising general-purpose registers storing data including results of operations of said instruction processor, address adders calculating the address of branch destination instructions by using data read out from the general-purpose register and an ALU performing arithmetical or logical operations on the data read out from the general-purpose register in the decode cycle of the instructions. The result of the arithmetical or logical operation is inputted into the address adder but not from the general-purpose register, in the case where the result of the arithmetical or logical operation is utilized for address calculation in the execution of a succeeding instruction.
    • 指令处理器对寄存器操作数进行操作并处理分支指令以执行分支目的地指令的地址计算,包括通用寄存器,其存储包括所述指令处理器的操作结果的数据,地址加法器通过使用数据计算分支目的地指令的地址 从通用寄存器读出,以及ALU对指令的解码周期中从通用寄存器读出的数据执行算术或逻辑运算。 在执行后续指令时,算术运算或逻辑运算的结果被用于地址计算的情况下,将算术或逻辑运算的结果输入到地址加法器而不是通用寄存器。