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1. 发明授权

US06699726B2 Semiconductor device and method for the manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06699726B2
公开(公告)日：2004-03-02
申请号：US10336012
申请日：2003-01-03
申请人： Osamu Hidaka , Sumito Ootsuki , Hiroshi Mochizuki , Hiroyuki Kanaya , Kumi Okuwada , Tomio Katata , Norihisa Arai , Hiroyuki Takenaka
发明人： Osamu Hidaka , Sumito Ootsuki , Hiroshi Mochizuki , Hiroyuki Kanaya , Kumi Okuwada , Tomio Katata , Norihisa Arai , Hiroyuki Takenaka
IPC分类号： H01G706
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76804 , H01L21/76834 , H01L21/7685 , H01L21/76895 , H01L23/5226 , H01L27/11502 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film. One of the drain region and the source region and one of the upper electrode and the lower electrode of the capacitor are connected to each other by an electrode wiring. A wiring connected to the other one of the drain region and the source region is formed on the semiconductor substrate.
摘要翻译：半导体器件以这样的方式构成，即在半导体衬底的表面层部分中形成具有由杂质扩散区域构成的漏极区域和源极区域的开关晶体管。在含有晶体管的半导体基板上形成第一绝缘膜，在第一绝缘膜的上层侧形成电容器。电容器包括下电极，包括铁电和高介电常数电介质之一的电极间绝缘膜和上电极。在形成电极间绝缘膜之前，形成第二绝缘膜以覆盖电极间绝缘膜的侧面部分，第二绝缘膜保护电极间绝缘膜的侧面部分。漏极区域和源极区域之一以及电容器的上部电极和下部电极中的一个通过电极布线彼此连接。在半导体衬底上形成连接到另一个漏极区域和源极区域的布线。

2. 发明授权

US06521927B2 Semiconductor device and method for the manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06521927B2
公开(公告)日：2003-02-18
申请号：US09102616
申请日：1998-06-23
申请人： Osamu Hidaka , Sumito Ootsuki , Hiroshi Mochizuki , Hiroyuki Kanaya , Kumi Okuwada , Tomio Katata , Norihisa Arai , Hiroyuki Takenaka
发明人： Osamu Hidaka , Sumito Ootsuki , Hiroshi Mochizuki , Hiroyuki Kanaya , Kumi Okuwada , Tomio Katata , Norihisa Arai , Hiroyuki Takenaka
IPC分类号： H01L31119
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76804 , H01L21/76834 , H01L21/7685 , H01L21/76895 , H01L23/5226 , H01L27/11502 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device is constituted in such a manner that a switching transistor having a drain region and a source region which are comprised of an impurity-diffused region is formed in the surface layer portion of a semiconductor substrate. On the semiconductor substrate containing the transistor, a first insulation film is formed, and, at the upper layer side of the first insulation film, a capacitor is formed. The capacitor is comprised of a lower electrode, an inter-electrode insulation film comprising one of ferroelectric and high-permittivity dielectric, and an upper electrode. Before the inter-electrode insulation film is formed, a second insulation film is formed so as to cover the side face portion of the inter-electrode insulation film, the second insulation film protecting the side face portion of the inter-electrode insulation film. One of the drain region and the source region and one of the upper electrode and the lower electrode of the capacitor are connected to each other by an electrode wiring. A wiring connected to the other one of the drain region and the source region is formed on the semiconductor. substrate.
摘要翻译：半导体器件以这样的方式构成，即在半导体衬底的表面层部分中形成具有由杂质扩散区域构成的漏极区域和源极区域的开关晶体管。在含有晶体管的半导体基板上形成第一绝缘膜，在第一绝缘膜的上层侧形成电容器。电容器包括下电极，包括铁电和高介电常数电介质之一的电极间绝缘膜和上电极。在形成电极间绝缘膜之前，形成第二绝缘膜以覆盖电极间绝缘膜的侧面部分，第二绝缘膜保护电极间绝缘膜的侧面部分。漏极区域和源极区域之一以及电容器的上部电极和下部电极中的一个通过电极布线彼此连接。在半导体上形成与漏极区域和源极区域中的另一个连接的布线。基质。

3. 发明授权

US06303958B1 Semiconductor integrated circuit and method for manufacturing the same 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06303958B1
公开(公告)日：2001-10-16
申请号：US09095890
申请日：1998-06-11
申请人： Hiroyuki Kanaya , Osamu Hidaka , Kumi Okuwada , Hiroshi Mochizuki
发明人： Hiroyuki Kanaya , Osamu Hidaka , Kumi Okuwada , Hiroshi Mochizuki
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a first hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.
摘要翻译：半导体集成电路具有铁电电容器。铁电电容器包括形成在半导体衬底上的第一绝缘膜，第一电极，其被埋在形成在第一绝缘膜中的表面平坦化的第一孔中，形成在第一绝缘膜上方的第二绝缘膜，在第二孔中形成的铁电膜，形成在第二孔中并在铁电体膜上方的第二电极，并且与第二绝缘膜的表面齐平。

4. 发明授权

US06750093B2 Semiconductor integrated circuit and method for manufacturing the same 失效
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06750093B2
公开(公告)日：2004-06-15
申请号：US10310954
申请日：2002-12-06
申请人： Hiroyuki Kanaya , Osamu Hidaka , Kumi Okuwada , Hiroshi Mochizuki
发明人： Hiroyuki Kanaya , Osamu Hidaka , Kumi Okuwada , Hiroshi Mochizuki
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.
摘要翻译：半导体集成电路具有铁电电容器。铁电电容器包括形成在半导体衬底上的第一绝缘膜，第一电极，其被埋在形成在第一绝缘膜中并且其表面平坦化的第一孔中;第二绝缘膜，形成在第一绝缘膜上方，并具有第二绝缘膜在第二孔中形成的铁电膜，形成在第二孔中并在铁电体膜上方的第二电极，并且与第二绝缘膜的表面齐平。

5. 发明授权

US06190957B1 Method of forming a ferroelectric device 失效
标题翻译：形成铁电体器件的方法
公开(公告)号：US06190957B1
公开(公告)日：2001-02-20
申请号：US09324501
申请日：1999-06-02
申请人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
发明人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
IPC分类号： H01L218242
CPC分类号： H01L27/11507 , H01L21/76895 , H01L27/10852 , H01L27/11502 , H01L28/55
摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线电容器接触插头。

6. 发明授权

US06511877B2 Semiconductor integrated circuit and method for manufacturing the same 有权
公开(公告)号：US06511877B2
公开(公告)日：2003-01-28
申请号：US09922074
申请日：2001-08-06
申请人： Hiroyuki Kanaya , Osamu Hidaka , Kumi Okuwada , Hiroshi Mochizuki
发明人： Hiroyuki Kanaya , Osamu Hidaka , Kumi Okuwada , Hiroshi Mochizuki
IPC分类号： H01L218242
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A semiconductor integrated circuit has a ferroelectric capacitor. The ferroelectric capacitor includes a first insulation film formed above a semiconductor substrate, a first electrode which is buried in a fist hole formed in the first insulation film and whose surface is flattened, a second insulation film formed above the first insulation film and having a second hole above the first electrode, a ferroelectric film formed in the second hole, and a second electrode formed in the second hole and above the ferroelectric film and flattened so as to be flush with a surface of the second insulation film.

7. 发明授权

US5990507A Semiconductor device having ferroelectric capacitor structures 失效
标题翻译：具有铁电电容器结构的半导体器件
公开(公告)号：US5990507A
公开(公告)日：1999-11-23
申请号：US889470
申请日：1997-07-08
申请人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
发明人： Hiroshi Mochizuki , Kumi Okuwada , Hiroyuki Kanaya , Osamu Hidaka , Susumu Shuto , Iwao Kunishima
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11507 , H01L21/76895 , H01L27/10852 , H01L27/11502 , H01L28/55
摘要： A method of manufacturing a semiconductor apparatus comprises the steps of forming, on a surface of a semiconductor substrate, an MIS transistor including a drain region and a source region each formed of an impurity diffusion region, forming an insulation film on the semiconductor substrate after the MIS transistor has been formed, selectively forming contact holes in the insulation film, embedding, into the contact hole, a capacitor contact plug having a lower end which is in contact with one of the drain region and the source region of the MIS transistor, forming a ferroelectric capacitor having a lower electrode, a ferroelectric film and an upper electrode on the insulation film after the capacitor contact plug has been formed, and forming an electric wire for establishing a connection between the upper electrode of the ferroelectric capacitor and an upper surface of the capacitor contact plug.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底的表面上形成包括漏区和源区的MIS晶体管，所述漏极区和源区各自由杂质扩散区形成，在所述半导体衬底之后形成绝缘膜 MIS晶体管已经形成，在绝缘膜中选择性地形成接触孔，将接触孔埋入电容器接触插塞中，该电容器接触插塞的下端与MIS晶体管的漏极区域和源极区域中的一个接触，形成在形成电容器接触插塞之后，在绝缘膜上形成具有下电极，铁电体膜和上电极的铁电电容器，并且形成用于建立铁电电容器的上电极和上电极之间的连接的电线电容器接触插头。

8. 发明授权

US07214595B2 Method of producing semiconductor devices 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07214595B2
公开(公告)日：2007-05-08
申请号：US10607216
申请日：2003-06-27
申请人： Atsuko Kawasaki , Satoshi Matsuda , Hisakazu Matsumori , Hidenori Shibata , Kumi Okuwada
发明人： Atsuko Kawasaki , Satoshi Matsuda , Hisakazu Matsumori , Hidenori Shibata , Kumi Okuwada
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/76224
摘要： A method of producing semiconductor devices is provided, which makes it possible to bury a silicon oxide without shape deterioration in device isolation trenches. The method comprises the steps of: forming an etching resistive mask over a semiconductor substrate; etching the semiconductor substrate through an opening in the etching resistive mask to form a device isolation trench; forming a coat of a silazane perhydride polymer solution over the semiconductor substrate having the device isolation trench formed therein; vaporizing a solvent from the coat and then subjecting the coat to chemical reaction to form a film of silicon oxide; removing said film of the silicon oxide leaving a residue inside said device isolation trench; and heating said silicon oxide left in said device isolation trench for densification.
摘要翻译：提供了一种制造半导体器件的方法，这使得可以在器件隔离沟槽中埋入氧化硅而没有形状劣化。该方法包括以下步骤：在半导体衬底上形成蚀刻电阻掩模; 通过蚀刻电阻掩模中的开口蚀刻半导体衬底以形成器件隔离沟槽; 在其上形成有器件隔离沟槽的半导体衬底上形成硅氮烷聚合物溶液涂层; 从涂层中蒸发溶剂，然后使涂层进行化学反应以形成氧化硅膜; 在所述器件隔离沟槽内去除留下残留物的所述氧化硅膜; 并加热留在所述器件隔离沟槽中的所述氧化硅用于致密化。

9. 发明授权

US5929473A MMIC semiconductor device with WN.sub.x capacitor electrode 失效
标题翻译：带有WNx电容电极的MMIC半导体器件
公开(公告)号：US5929473A
公开(公告)日：1999-07-27
申请号：US842646
申请日：1997-04-15
申请人： Kazuya Nishihori , Yoshiaki Kitaura , Yoshikazu Tanabe , Tomonori Aoyama , Kyoichi Suguro , Kumi Okuwada , Shuichi Komatsu , Kazuhide Abe
发明人： Kazuya Nishihori , Yoshiaki Kitaura , Yoshikazu Tanabe , Tomonori Aoyama , Kyoichi Suguro , Kumi Okuwada , Shuichi Komatsu , Kazuhide Abe
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/06 , H01L27/095 , H01L29/92 , H01L29/812
CPC分类号： H01L27/0629 , H01L27/0605 , H01L27/10852 , H01L28/40
摘要： An SiO.sub.2 film and a first wiring layer are arranged in this order on a GaAs substrate. A capacitor is formed on the first wiring layer. The capacitor includes a lower electrode which has a multi-layer structure consisting of a Ti layer, an Mo layer, and a Pt layer in this order from underside. The capacitor also includes a dielectric film made of strontium titanate. The capacitor further includes an upper electrode which has a multi-layer structure consisting of a WN.sub.x layer (120 nm) and a W layer (300 nm) in this order from underside. That surface of the upper electrode, which is in contact with the dielectric film, is defined by the tungsten nitride layer.
摘要翻译：在GaAs衬底上依次排列有SiO 2膜和第一布线层。在第一布线层上形成电容器。电容器包括从下侧依次具有由Ti层，Mo层和Pt层构成的多层结构的下电极。电容器还包括由钛酸锶制成的电介质膜。电容器还包括从下侧依次具有由WNx层（120nm）和W层（300nm）构成的多层结构的上部电极。与电介质膜接触的上电极的表面由氮化钨层限定。

10. 发明授权

US5164882A Ceramic capacitor 失效
标题翻译：陶瓷电容器
公开(公告)号：US5164882A
公开(公告)日：1992-11-17
申请号：US808674
申请日：1991-12-17
申请人： Hideyuki Kanai , Yohachi Yamashita , Osamu Furukawa , Kumi Okuwada
发明人： Hideyuki Kanai , Yohachi Yamashita , Osamu Furukawa , Kumi Okuwada
IPC分类号： C04B35/49 , C04B35/491 , H01B3/12 , H01G4/12
CPC分类号： H01G4/1245 , C04B35/491
摘要： A ceramic capacitor includes at least two opposing electrodes, and a dielectric ceramic composition arranged between the electrodes, wherein the ceramic composition is represented by a formula (Pb.sub.1-x Ae.sub.x) (Zr.sub.1-y Ti.sub.y)O.sub.3 (wherein x represents 0.15 to 0.90, y represents 0 to 0.80, and Ae represents at least one type of an element selected from the group consisting of Ca and Sr), and has a composition in which assuming that the total number of moles of elements constituting a site A consisting of Pb and Ae is (A) and that the total number of moles of elements constituting a site B consisting of Zr and Ti is (B), (A)/(B) is 1.00 or less. The site A of the dielectric ceramic composition may be partially substituted with Ba. The dielectric ceramic composition may be obtained by adding Nb, Cu, Bi, Mn, Co, Ag, Si, Ta, Mg, Zn, W and/or Ni to a composition which is represented by a formula (Pb.sub.1-x Ae.sub.x) (Zr.sub.1-y Ti.sub.y)O.sub.3 (wherein x represents 0.15 to 0.90, y represents 0 to 0.80, and Ae represents at least one type of an element selected from the group consisting of Ca, Sr, and Ba), and in which assuming that the total number of moles of elements constituting a site A consisting of Pb and Ae is (A) and that the total number of moles of elements constituting a site B consisting of Zr and Ti is (B), (A)/(B) is 1.00 or less. The dielectric ceramic composition is preferably formed by using a powder synthesized by a hydrothermal synthesis as a material, and its grain size is preferably 3 .mu.m or less.
摘要翻译：陶瓷电容器包括至少两个相对的电极和布置在电极之间的介电陶瓷组合物，其中陶瓷组合物由式（Pb1-xAex）（Zr1-yTiO）O3表示（其中x表示0.15至0.90，y表示 0〜0.80，Ae表示选自Ca和Sr中的至少一种元素），并且具有假定构成由Pb和Ae构成的位点A的元素的总摩尔数为（A），构成由Zr和Ti构成的部位B的元素的总摩尔数为（B），（A）/（B）为1.00以下。电介质陶瓷组合物的位置A可以部分地被Ba取代。介电陶瓷组合物可以通过将Nb，Cu，Bi，Mn，Co，Ag，Si，Ta，Mg，Zn，W和/或Ni添加到由式（Pb1-xAex）（Zr1 -yTiy）O 3（其中x表示0.15〜0.90，y表示0〜0.80，Ae表示选自Ca，Sr和Ba中的至少一种元素），其中假设总数构成由Pb和Ae构成的部位A的元素的摩尔数为（A），构成由Zr和Ti构成的部位B的元素的总摩尔数为（B），（A）/（B）为1.00或减。电介质陶瓷组合物优选通过使用通过水热合成合成的粉末作为材料形成，其粒径优选为3μm以下。

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