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1. 发明授权

US06493268B1 Circuit device for performing hierarchic row decoding in non-volatile memory devices 有权
标题翻译：用于在非易失性存储器件中执行分级行解码的电路装置
公开(公告)号：US06493268B1
公开(公告)日：2002-12-10
申请号：US09905163
申请日：2001-07-12
申请人： Osama Khouri , Andrea Pierin , Rino Micheloni , Stefano Gregori , Guido Torelli , Miriam Sangalli
发明人： Osama Khouri , Andrea Pierin , Rino Micheloni , Stefano Gregori , Guido Torelli , Miriam Sangalli
IPC分类号： G11C1600
CPC分类号： G11C16/08
摘要： A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.
摘要翻译：一种用于在非易失性类型的半导体存储器件中执行分级行解码的电路装置，该存储器件包括具有列排列扇区的存储器单元阵列，其中每个扇区具有链接到主字线的相应组的本地字线。电路装置包括在每个主字线处提供的主字线驱动器和在每个本地字线处提供的本地解码器。该电路装置还包括对于每个主字线，连接在相关联的本地字线的主字线和本地解码器之间的专用路径，并连接到布置成接收读/写电压的外部端子，该专用路径使得能够传送读/编程电压到本地解码器。

2. 发明授权

US06788579B2 Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude 有权
标题翻译：使用程序和验证算法编程非易失性存储单元的方法，使用具有不同步长幅度的阶梯电压
公开(公告)号：US06788579B2
公开(公告)日：2004-09-07
申请号：US10119523
申请日：2002-04-09
申请人： Stefano Gregori , Rino Micheloni , Andrea Pierin , Osama Khouri , Guido Torelli
发明人： Stefano Gregori , Rino Micheloni , Andrea Pierin , Osama Khouri , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C16/12
摘要： A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.
摘要翻译：用于编程非易失性存储器单元的方法设想连续地应用到存储器单元的栅极端，第一和第二编程脉冲串，其阶梯形式的脉冲幅度增加，其中在一个脉冲和下一个脉冲之间的振幅增量第一编程脉冲序列大于第二编程脉冲串中的一个脉冲和下一个脉冲之间的振幅增量。编程方法设想在存储器单元的栅极端子和第一编程脉冲串之前施加具有阶梯式脉冲幅度增加的第三编程脉冲串，其中，一个脉冲与下一个脉冲之间的振幅增量可能小于第一编程脉冲序列中的振幅增量基本上等于第二编程脉冲串中的幅度增量，或者可以大于第一编程脉冲序列中的振幅增量。

3. 发明授权

US06542404B2 Small size, low consumption, multilevel nonvolatile memory 有权
标题翻译：小尺寸，低功耗，多级非易失性存储器
公开(公告)号：US06542404B2
公开(公告)日：2003-04-01
申请号：US09972726
申请日：2001-10-04
申请人： Andrea Pierin , Stefano Gregori , Rino Micheloni , Osama Khouri , Guido Torelli
发明人： Andrea Pierin , Stefano Gregori , Rino Micheloni , Osama Khouri , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C16/30 , G11C5/145 , G11C7/06 , G11C11/5621 , G11C11/5642 , G11C16/26
摘要： A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).
摘要翻译：多级非易失性存储器包括提供电源电压（VDD）的电源线（28），提供高于电源电压（VDD）的升压电压（Vp）的升压电路（26），连接的升压线路到升压电路（26）和包括至少一个比较器（35）的读取电路（25）。比较器（35）包括第一和第二输入（35a，35b），第一和第二输出（45a，45b），连接到升压线（30）的至少一个放大级（40）线路锁存级（41）连接到电源线（28）。

4. 发明授权

US06674385B2 Analog-to-digital conversion method and device, in high-density multilevel non-volatile memory devices 有权
标题翻译：模数转换方法和器件，在高密度多级非易失性存储器件中
公开(公告)号：US06674385B2
公开(公告)日：2004-01-06
申请号：US10060076
申请日：2002-01-29
申请人： Rino Micheloni , Osama Khouri , Andrea Pierin , Stefano Gregori , Guido Torelli
发明人： Rino Micheloni , Osama Khouri , Andrea Pierin , Stefano Gregori , Guido Torelli
IPC分类号： H03M112
CPC分类号： G11C11/56 , G11C27/005 , H03M1/146 , H03M1/361
摘要： An analog-to-digital conversion method and device for a multilevel non-volatile memory device that includes a multilevel memory cell. The method comprises a first step of converting the most significant bits contained in the memory cell, followed by a second step of converting the least significant bits. The first step is completed within a time interval corresponding to the rise transient of the gate voltage, and the second step is initiated at the end of the transient. Also disclosed is a scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different “bit-layers”, which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is achieved by using a simple error control code providing single-bit correction, regardless of the number of bits stored in a single cell.
摘要翻译：一种用于包括多电平存储器单元的多级非易失性存储器件的模数转换方法和装置。该方法包括转换存储单元中包含的最高有效位的第一步骤，随后转换最低有效位的第二步骤。在对应于栅极电压的上升瞬变的时间间隔内完成第一步，并且在瞬态结束时启动第二步。还公开了一种用于多电平闪存中的错误控制编码的方案。存储在单个存储器单元中的n位被组织在彼此独立的不同“位层”中。针对每个位层分别执行错误校正。通过使用提供单位校正的简单误差控制代码来实现单个存储器单元中的任何故障的校正，而不管存储在单个单元中的位数。

5. 发明授权

US06404273B1 Voltage booster with a low output resistance 有权
标题翻译：电压增压器具有低输出电阻
公开(公告)号：US06404273B1
公开(公告)日：2002-06-11
申请号：US09785083
申请日：2001-02-13
申请人： Stefano Gregori , Osama Khouri , Andrea Pierin , Rino Micheloni , Guido Torelli , Dario Soltesz
发明人： Stefano Gregori , Osama Khouri , Andrea Pierin , Rino Micheloni , Guido Torelli , Dario Soltesz
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/075
摘要： A charge pump voltage booster circuit for generating, from a first voltage supplied at the input to the circuit, an output voltage with an absolute value that is higher than the first voltage, comprises at least one stage having a charge pass element and a charge storage capacitor with a first plate connected to an output of the charge pass element and a second plate controlled by a square-wave control signal of period varying between a reference voltage and the first voltage, supplied to the second plate of the capacitor by means of a driver circuit comprising a pull-up transistor and a pull-down transistor connected in series between the first voltage and the reference voltage. Means of overdriving at least one of the said transistors, either the pull-up transistor or the pull-down transistor, supply to the said at least one transistor a firing control voltage that has a higher absolute value than the first voltage.
摘要翻译：一种电荷泵升压电路，用于根据从所述电路的输入端提供的第一电压产生具有高于所述第一电压的绝对值的输出电压，所述电压泵电压升压电路包括至少一个具有充电通路元件和电荷存储器电容器，其具有连接到所述电荷通过元件的输出端的第一板，以及第二板，其由在基准电压和所述第一电压之间变化的周期的方波控制信号控制，所述方波控制信号通过驱动器电路包括串联在第一电压和参考电压之间的上拉晶体管和下拉晶体管。过载驱动所述晶体管中的至少一个（上拉晶体管或下拉晶体管）的装置向所述至少一个晶体管提供具有比第一电压更高的绝对值的点火控制电压。

6. 发明授权

US06480421B2 Circuit for reading non-volatile memories 有权
标题翻译：用于读取非易失性存储器的电路
公开(公告)号：US06480421B2
公开(公告)日：2002-11-12
申请号：US10003474
申请日：2001-10-25
申请人： Khouri Osama , Stefano Gregori , Andrea Pierin , Rino Micheloni , Sergio Coronini , Guido Torelli
发明人： Khouri Osama , Stefano Gregori , Andrea Pierin , Rino Micheloni , Sergio Coronini , Guido Torelli
IPC分类号： G11C1606
CPC分类号： G11C27/005 , G11C7/062 , G11C11/5642 , G11C16/28 , G11C2207/063
摘要： A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.
摘要翻译：用于读取非易失性存储单元的电路具有用于提供输出电流的输出端子和用于接收用于控制输出电流的电压的控制端子。读取电路包括可以与输出端子和控制端子电连接以从参考信号和输出电流产生控制电压的反馈电路。反馈电路还包括电流放大电路，其具有用于接收从参考信号和输出电流导出的电流 - 误差信号的第一端子和用于提供放大电流的第二端子。

7. 发明授权

US07047478B2 Multipurpose method for constructing an error-control code for multilevel memory cells operating with a variable number of storage levels, and multipurpose error-control method using said error-control code 失效
标题翻译：用于构建以可变数量的存储级别操作的多级存储器单元的错误控制代码的多用途方法，以及使用所述错误控制代码的多用途错误控制方法
公开(公告)号：US07047478B2
公开(公告)日：2006-05-16
申请号：US10015949
申请日：2001-11-02
申请人： Stefano Gregori , Pietro Ferrari , Guido Torelli
发明人： Stefano Gregori , Pietro Ferrari , Guido Torelli
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/00 , G11C2211/5641
摘要： Described is an error control method for multilevel memory cells operating with a variable number of storage levels. The method includes: receiving a first information word having k input symbols each in a first base; converting the first information word into a second base by converting the input symbols into input symbols in the second base; encoding the converted first information word into a first codeword having k+n coded symbols in the second base; and writing the first codeword into the multilevel memory cells. The encoding step may include generating a generating matrix and multiplying the first information word by the generating matrix to produce the first codeword.
摘要翻译：描述了对具有可变数量的存储级别操作的多级存储器单元的错误控制方法。该方法包括：在第一基站中接收具有k个输入符号的第一信息字; 通过将输入符号转换为第二基底中的输入符号将第一信息字转换成第二基底; 将转换的第一信息字编码为在第二基底中具有k + n个编码符号的第一码字; 以及将所述第一码字写入所述多层存储器单元。编码步骤可以包括生成生成矩阵并将第一信息字乘以生成矩阵以产生第一码字。

8. 发明申请

US20070076890A1 Current flattening and current sensing methods and devices 失效
标题翻译：当前的扁平化和电流检测方法和装置
公开(公告)号：US20070076890A1
公开(公告)日：2007-04-05
申请号：US11509036
申请日：2006-08-24
申请人： Radu Muresan , Stefano Gregori
发明人： Radu Muresan , Stefano Gregori
IPC分类号： H04K1/00
CPC分类号： H04L9/0625 , G09C1/00 , H04L9/003 , H04L2209/12 , H04L2209/125 , H04L2209/127
摘要： Flattening total current consumption of system having processing core and power supply input by current sensing within system at power supply input and controlling system current consumption such that system current is reduced if over reference current threshold, and increased if below reference current threshold. Inject additional current through digital injections cells working higher frequencies, by increasing switching activity, by increasing voltage supply to core, and by increasing operating frequency of processor core. Feedback signal indicates current consumption of system. Current consumption similarly decreased. Current sensed by mirroring input current inline with power supply input and compensating for voltage drop introduced by mirroring using opposing field effect transistors and maintaining outputs at same voltage through feedback control loop. Processor core may be general purpose processor core or cryptographic processor core. System may be system-on-chip or system-on-package. System includes processor core and current flattening device based on method. Also, current flattening device and current sensor. On chip current sensor sensing current draw of processor core.
摘要翻译：通过电源输入和控制系统的电流消耗使系统内的电流检测系统的整体电流消耗达到整体系统的电流消耗，如果超过参考电流阈值，则系统电流降低，如果低于参考电流阈值则增加。通过数字注入单元工作更高频率，通过增加开关活动，增加对核心的电压供应以及增加处理器内核的工作频率来注入额外的电流。反馈信号表示系统的电流消耗。电流消耗同样下降。通过将输入电流与电源输入串联在一起而检测的电流，并补偿通过使用相反的场效应晶体管进行镜像引入的电压降，并通过反馈控制回路将输出保持在相同的电压。处理器核心可以是通用处理器核心或加密处理器核心。系统可以是片上系统或系统级封装。系统包括基于方法的处理器核心和当前平坦化设备。此外，目前的扁平装置和电流传感器。片上电流传感器感应电流的处理器内核。

9. 发明授权

US07716502B2 Current flattening and current sensing methods and devices 失效
标题翻译：当前的扁平化和电流检测方法和装置
公开(公告)号：US07716502B2
公开(公告)日：2010-05-11
申请号：US11509036
申请日：2006-08-24
申请人： Radu Muresan , Stefano Gregori
发明人： Radu Muresan , Stefano Gregori
IPC分类号： G06F1/26
CPC分类号： H04L9/0625 , G09C1/00 , H04L9/003 , H04L2209/12 , H04L2209/125 , H04L2209/127
摘要： Flattening total current consumption of system having processing core and power supply input by current sensing within system at power supply input and controlling system current consumption such that system current is reduced if over reference current threshold, and increased if below reference current threshold. Inject additional current through digital injections cells working higher frequencies, by increasing switching activity, by increasing voltage supply to core, and by increasing operating frequency of processor core. Feedback signal indicates current consumption of system. Current consumption similarly decreased. Current sensed by mirroring input current inline with power supply input and compensating for voltage drop introduced by mirroring using opposing field effect transistors and maintaining outputs at same voltage through feedback control loop. Processor core may be general purpose processor core or cryptographic processor core. System may be system-on-chip or system-on-package. System includes processor core and current flattening device based on method. Also, current flattening device and current sensor. On chip current sensor sensing current draw of processor core.
摘要翻译：通过电源输入和控制系统的电流消耗使系统内的电流检测系统的整体电流消耗达到整体系统的电流消耗，如果超过参考电流阈值，则系统电流降低，如果低于参考电流阈值则增加。通过数字注入单元工作更高频率，通过增加开关活动，增加对核心的电压供应以及增加处理器内核的工作频率来注入额外的电流。反馈信号表示系统的电流消耗。电流消耗同样下降。通过将输入电流与电源输入串联在一起而检测的电流，并补偿通过使用相反的场效应晶体管进行镜像引入的电压降，并通过反馈控制回路将输出保持在相同的电压。处理器核心可以是通用处理器核心或加密处理器核心。系统可以是片上系统或系统级封装。系统包括基于方法的处理器核心和当前平坦化设备。此外，目前的扁平装置和电流传感器。片上电流传感器感应电流的处理器内核。

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