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2. 发明授权

US06223257B1 Instruction cache address generation technique having reduced delays in fetching missed data 失效
标题翻译：指令高速缓存地址生成技术减少了提取丢失数据的延迟
公开(公告)号：US06223257B1
公开(公告)日：2001-04-24
申请号：US09310659
申请日：1999-05-12
申请人： Sean P. Cummins , Kenneth K. Munson , Christopher I. W. Norrie , Matthew D. Ornes
发明人： Sean P. Cummins , Kenneth K. Munson , Christopher I. W. Norrie , Matthew D. Ornes
IPC分类号： G06F1212
CPC分类号： G06F9/3802 , G06F12/0859
摘要： A technique and system for reading instruction data from a cache memory with minimum delays. Addresses are calculated and applied to the cache memory in two or more cycles by a pipelined address generation circuit. While data at one address is being retrieved, the next address is being calculated. It is presumed, when calculating the next address, that the current address will return all the data it is addressing. In response to a miss signal received from the cache when no data at the current address is in the cache, the missed data is read from a main system memory and accessed with improved speed. In a system where the cache memory and processor operate at a higher clock frequency than the main system memory, new data is obtained from the main memory during only periodically occurring cache clock cycles. A missed cache memory address is regenerated in a manner to access such new data during the same cache clock cycle that it first becomes available from the main memory. This eliminates the occurrence of penalty delay cycles that reduce the rate at which instructions are issued in existing processors, and thus improves the speed of operation of the processors.
摘要翻译：一种用于以最小延迟从高速缓冲存储器读取指令数据的技术和系统。地址由流水线地址产生电路计算并在两个或多个周期内应用于高速缓冲存储器。虽然正在检索一个地址的数据，但是正在计算下一个地址。假设当计算下一个地址时，当前地址将返回其正在寻址的所有数据。响应于当高速缓存中没有当前地址上的数据时从高速缓存接收到的未命中信号，从主系统存储器读取丢失的数据并以改进的速度访问。在高速缓冲存储器和处理器以比主系统存储器更高的时钟频率工作的系统中，仅在周期性发生的高速缓存时钟周期期间从主存储器获得新的数据。错过的高速缓存存储器地址以在首次从主存储器可用的相同高速缓存时钟周期内访问这样的新数据的方式被重新生成。这消除了降低在现有处理器中发出指令的速率的惩罚延迟周期的发生，并因此提高了处理器的操作速度。

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