专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050026345A1 PROCESS FOR FORMING DUAL METAL GATE STRUCTURES 有权
标题翻译：形成双金属门结构的方法
公开(公告)号：US20050026345A1
公开(公告)日：2005-02-03
申请号：US10632473
申请日：2003-07-31
申请人： Olubunmi Adetutu , Hsing Tseng , Wei Wu
发明人： Olubunmi Adetutu , Hsing Tseng , Wei Wu
IPC分类号： H01L21/8238 , H01L21/338
CPC分类号： H01L21/823842
摘要： A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.
摘要翻译：半导体器件具有包括第一金属类型的第一金属类型和第二金属类型的P沟道栅极堆叠以及包括与栅极电介质/蚀刻停止层堆叠直接接触的第二金属类型的N沟道栅极堆叠。通过干蚀刻蚀刻N沟道栅极堆叠和P沟道栅极堆叠。栅极电介质或蚀刻停止件可以与衬底接触。蚀刻停止层防止第一和第二金属层的干蚀刻蚀刻通过栅极电介质并且刨削下面的衬底。

2. 发明申请

US20060273411A1 In-situ nitridation of high-k dielectrics 有权
标题翻译：高k电介质的原位氮化
公开(公告)号：US20060273411A1
公开(公告)日：2006-12-07
申请号：US11146826
申请日：2005-06-07
申请人： Dina Triyoso , Olubunmi Adetutu , Hsing Tseng
发明人： Dina Triyoso , Olubunmi Adetutu , Hsing Tseng
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L29/513 , H01L29/518 , H01L29/78
摘要： A semiconductor fabrication process for forming a gate dielectric includes depositing a high-k dielectric stack including incorporating nitrogen into the high-k dielectric stack in-situ. A top high-k dielectric is formed overlying the dielectric stack and the dielectric stack and the top dielectric are annealed. Depositing the dielectric stack may include depositing a plurality of high-k dielectric layers where each layer is formed in a distinct processing step or set of steps. Depositing one of the dielectric layers may include performing a plurality of atomic layer deposition processes to form a plurality of high-k sublayers, wherein each sublayer is a monolayer film. Depositing the plurality of sublayers may include depositing a nitrogen free sublayer and depositing a nitrogen bearing sublayer. Depositing the nitrogen free sublayer may include pulsing an ALD chamber with HfCl4, purging the chamber with an inert, pulsing the chamber with an H2O or D2O, and purging the chamber with an inert.
摘要翻译：用于形成栅极电介质的半导体制造工艺包括沉积高k电介质堆叠，其包括将氮掺杂到原位的高k电介质堆叠中。形成覆盖在电介质堆叠上的顶部高k电介质，并且电介质堆叠和顶部电介质被退火。沉积介质堆叠可以包括沉积多个高k电介质层，其中每个层以不同的处理步骤或一组步骤形成。沉积一个电介质层可以包括执行多个原子层沉积工艺以形成多个高k子层，其中每个子层是单层膜。沉积多个子层可以包括沉积无氮的子层并沉积含氮的子层。沉积无氮子层可以包括用HfCl 4脉冲发射ALD室，用惰性气体冲洗室，用H 2 O 2或D 2 并且用惰性气体清洗室。

3. 发明申请

US20060094259A1 Forming gas anneal process for high dielectric constant gate dielectrics in a semiconductor fabrication process 审中-公开
标题翻译：在半导体制造工艺中形成用于高介电常数栅极电介质的气体退火工艺
公开(公告)号：US20060094259A1
公开(公告)日：2006-05-04
申请号：US10980445
申请日：2004-11-03
申请人： David Gilmer , Olubunmi Adetutu , Hsing Tseng
发明人： David Gilmer , Olubunmi Adetutu , Hsing Tseng
IPC分类号： H01L21/4763 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02318 , H01L21/02123 , H01L21/02178 , H01L21/02181 , H01L21/28185 , H01L21/31645 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A semiconductor fabrication annealing process includes depositing a high dielectric constant gate dielectric over a substrate and annealing the gate dielectric. Annealing the gate dielectric includes exposing the gate dielectric to an inert ambient and ramping the inert ambient to an annealing temperature. A passivating gas is then introduced into the ambient while maintaining the ambient at the annealing temperature. This passivating ambient is then maintained at the annealing temperature for a specified duration. While maintaining the presence of the passivating gas in the ambient, the ambient temperature is then ramped down from the annealing temperature to a second temperature, which is preferably less than 100° C. The passivating gas is preferably hydrogen gas, deuterium gas, or a combination of the two. The annealing temperature is preferably greater than approximately 470° C.
摘要翻译：半导体制造退火工艺包括在衬底上沉积高介电常数栅极电介质并退火栅极电介质。对栅极电介质进行退火包括将栅极电介质暴露于惰性环境，并将惰性环境升温至退火温度。然后将钝化气体引入环境中，同时保持环境处于退火温度。然后将该钝化环境在退火温度下保持规定的持续时间。在保持环境中的钝化气体的存在的同时，环境温度然后从退火温度下降到第二温度，其优选小于100℃。钝化气体优选为氢气，氘气或两者的结合。退火温度优选大于约470℃

4. 发明申请

US20060234436A1 Method of forming a semiconductor device having a high-k dielectric 审中-公开
标题翻译：形成具有高k电介质的半导体器件的方法
公开(公告)号：US20060234436A1
公开(公告)日：2006-10-19
申请号：US11106797
申请日：2005-04-15
申请人： Hsing Tseng , Olubunmi Adetutu , David Gilmer
发明人： Hsing Tseng , Olubunmi Adetutu , David Gilmer
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/31
CPC分类号： H01L21/28185 , H01L21/02175 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： A metal oxide is formed over a high quality oxide which has been deposited over a substrate. An anneal drives a reaction to form a metal oxysilicon nitride layer which is then used as a part of a gate stack. The novel integration scheme allows for improved scalablity of devices as well as improved leakage currents.
摘要翻译：金属氧化物在已经沉积在衬底上的高质量氧化物上形成。退火驱动反应以形成金属氧氮化硅层，然后将其用作栅极堆叠的一部分。该新颖的集成方案允许改善器件的可扩展性以及改进的漏电流。

5. 发明申请

US20060220157A1 Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors 有权
标题翻译：过渡介电层提高高介电常数晶体管的可靠性和性能
公开(公告)号：US20060220157A1
公开(公告)日：2006-10-05
申请号：US11096515
申请日：2005-03-31
申请人： Sriram Kalpat , Voon-Yew Thean , Hsing Tseng , Olubunmi Adetutu
发明人： Sriram Kalpat , Voon-Yew Thean , Hsing Tseng , Olubunmi Adetutu
IPC分类号： H01L29/78 , H01L21/469
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L29/513 , H01L29/517
摘要： A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon. Forming the transitional dielectric layer (205) may include performing multiple cycles of an atomic layer deposition process (500) where a precursor concentration for each cycle differs from the precursor concentration of the preceding cycle.
摘要翻译：栅极电介质结构（201）制造工艺包括形成覆盖氧化硅膜（204）的过渡电介质膜（205）。然后形成覆盖在过渡介电膜（205）的上表面上的高介电常数膜（206）。氧化硅膜（204）界面处的过渡电介质膜（205）的组成主要包括硅和氧。高K电介质（206）和上表面附近的过渡电介质膜（205）的组成主要包括金属元素和氧。形成过渡电介质膜（205）可以包括形成多个过渡电介质层（207），其中每个连续的过渡介电层（207）的组成具有较高的金属元素浓度和较低的硅浓度。形成过渡电介质层（205）可以包括执行原子层沉积工艺（500）的多个循环，其中每个循环的前体浓度与先前循环的前体浓度不同。

6. 发明申请

US20050085092A1 Multi-layer dielectric containing diffusion barrier material 有权
标题翻译：多层电介质含有扩散阻挡材料
公开(公告)号：US20050085092A1
公开(公告)日：2005-04-21
申请号：US10687271
申请日：2003-10-16
申请人： Olubunmi Adetutu , Tien Luo , Hsing Tseng
发明人： Olubunmi Adetutu , Tien Luo , Hsing Tseng
IPC分类号： H01L21/28 , H01L21/469 , H01L29/51
CPC分类号： H01L21/28202 , H01L29/513 , H01L29/518
摘要： A method for forming a dielectric is disclosed. The method comprises forming a first dielectric layer over semiconductor material. A diffusion barrier material is introduced into the first dielectric layer. Lastly, a second dielectric layer is formed over the first dielectric layer after the introducing.
摘要翻译：公开了形成电介质的方法。该方法包括在半导体材料上形成第一介电层。扩散阻挡材料被引入到第一介电层中。最后，在引入之后，在第一电介质层上形成第二电介质层。

7. 发明申请

US20060194423A1 Method of making a nitrided gate dielectric 失效
标题翻译：制造氮化栅极电介质的方法
公开(公告)号：US20060194423A1
公开(公告)日：2006-08-31
申请号：US11067257
申请日：2005-02-25
申请人： Sangwoo Lim , Paul Grudowski , Tien Luo , Olubunmi Adetutu , Hsing Tseng
发明人： Sangwoo Lim , Paul Grudowski , Tien Luo , Olubunmi Adetutu , Hsing Tseng
IPC分类号： H01L21/3205 , H01L21/31 , H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译：用氮化步骤和退火处理栅极电介质。之后，进行另外的氮化步骤和退火。第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。

8. 发明申请

US20060084217A1 Plasma impurification of a metal gate in a semiconductor fabrication process 审中-公开
标题翻译：半导体制造工艺中的金属栅极的等离子体杂质化
公开(公告)号：US20060084217A1
公开(公告)日：2006-04-20
申请号：US10969486
申请日：2004-10-20
申请人： Tien Luo , Olubunmi Adetutu , Hsing Tseng
发明人： Tien Luo , Olubunmi Adetutu , Hsing Tseng
IPC分类号： H01L21/4763
CPC分类号： H01L21/76888 , H01L21/28088 , H01L21/28176 , H01L21/823842 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor fabrication includes forming a gate dielectric overlying a semiconductor substrate and depositing a metal gate film overlying the gate dielectric. Following deposition of the metal gate film, nitrogen, carbon, and/or oxygen is introduced into the metal gate film by exposing the metal gate film to a nitrogen, carbon, and/or oxygen bearing plasma. Thereafter, the nitrogenated/oxygenated/carbonated metal gate film is patterned to form a transistor gate electrode. Depositing the metal gate film is preferably done with a low energy process such as atomic layer deposition (ALD) or metal organic chemical vapor deposition (MOCVD) to reduce damage to the underlying gate dielectric. The metal gate film for NMOS devices is preferably a compound of nitrogen and Ti, W, or Ta. A second metal gate film may be used for PMOS devices. This second metal gate film is preferably a compound of oxygen and Ir, Ru, Mo, or Re.
摘要翻译：半导体制造包括形成覆盖在半导体衬底上的栅极电介质并沉积覆盖栅极电介质的金属栅极膜。在金属栅极膜沉积之后，通过将金属栅极膜暴露于氮，碳和/或含氧等离子体，将氮，碳和/或氧引入金属栅极膜。此后，对氮化/氧化/碳酸化的金属栅极膜进行构图以形成晶体管栅电极。优选地，通过诸如原子层沉积（ALD）或金属有机化学气相沉积（MOCVD）的低能量过程来沉积金属栅极膜以减少对下面的栅极电介质的损伤。用于NMOS器件的金属栅极膜优选为氮和Ti，W或Ta的化合物。 PMOS器件可以使用第二金属栅极膜。该第二金属栅极膜优选为氧和Ir，Ru，Mo或Re的化合物。

9. 发明申请

US20070042546A1 Method for forming floating gates within NVM process 有权
标题翻译：在NVM过程中形成浮动门的方法
公开(公告)号：US20070042546A1
公开(公告)日：2007-02-22
申请号：US11208670
申请日：2005-08-22
申请人： Jeffrey Thomas , Olubunmi Adetutu
发明人： Jeffrey Thomas , Olubunmi Adetutu
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/28273 , H01L27/115 , H01L27/11521
摘要： A semiconductor process and apparatus includes forming a semiconductor device by depositing a layer of nitride (20) over a semiconductor structure (10), patterning and etching the nitride layer to form a patterned nitride layer (42, 44), depositing a layer of polysilicon (62), planarizing the polysilicon layer with a CMP process to remove any portion of the polysilicon layer (62) above the patterned dielectric layer (42, 44), and then removing the patterned nitride layer (42, 44), thereby defining one or more polysilicon features (72, 74, 76) that can be used as floating gates, transistors gates, bit lines or any other semiconductor device feature.
摘要翻译：半导体工艺和设备包括通过在半导体结构（10）上沉积氮化物层（20）来形成半导体器件，图案化和蚀刻氮化物层以形成图案化氮化物层（42,44），沉积多晶硅层（62），用CMP工艺平坦化多晶硅层，以去除图案化的介电层（42,44）上方的多晶硅层（62）的任何部分，然后去除图案化的氮化物层（42,44），由此限定一个或更多个可用作浮动栅极，晶体管栅极，位线或任何其它半导体器件特征的多晶硅特征（72,74,76）。

10. 发明申请

US20060110892A1 Semiconductor process for forming stress absorbent shallow trench isolation structures 有权
标题翻译：用于形成应力吸收性浅沟槽隔离结构的半导体工艺
公开(公告)号：US20060110892A1
公开(公告)日：2006-05-25
申请号：US10996319
申请日：2004-11-22
申请人： Marius Orlowski , Mark Foisy , Olubunmi Adetutu
发明人： Marius Orlowski , Mark Foisy , Olubunmi Adetutu
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76224 , H01L21/76229 , H01L21/823807 , H01L21/823878
摘要： A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.
摘要翻译：半导体制造工艺包括在半导体衬底上图案化硬掩模以暴露隔离区域并在隔离区域中形成沟槽。在沟槽中沉积可流动电介质以部分地填充沟槽，并且覆盖覆盖第一氧化物的覆盖电介质以填充沟槽。衬底可以是包括掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底，并且沟槽可以部分地延伸到BOX层中。可流动电介质可以是自旋沉积的可流动氧化物或CVD BPSG氧化物。可流动介电隔离结构提供了缓冲器，其防止在隔离结构的一侧上引起的应力在结构的另一侧上产生应力。因此，例如，通过在PMOS区域中的硅上形成硅锗产生的压缩应力在NMOS区域中不产生压应力。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式