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1. 发明申请

US20070128868A1 ELECTROPLATING AND ELECTROLESS PLATING OF CONDUCTIVE MATERIALS INTO OPENINGS, AND STRUCTURES OBTAINED THEREBY 有权
标题翻译：导电材料的电镀和电镀镀层开放，并获得结构
公开(公告)号：US20070128868A1
公开(公告)日：2007-06-07
申请号：US11548053
申请日：2006-10-10
申请人： Patrick Halahan , Sam Kao , Bosco Lan , Sergey Savastiouk , Oleg Siniaguine
发明人： Patrick Halahan , Sam Kao , Bosco Lan , Sergey Savastiouk , Oleg Siniaguine
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76873 , H01L21/76874 , H01L21/76898 , H01L23/481 , H01L23/53238 , H01L2924/0002 , Y10S438/977 , H01L2924/00012 , H01L2924/00
摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.
摘要翻译：在包括半导体衬底（110）的晶片（104）中形成通孔（114）。种子层（610）溅射在晶片的底表面上。种子不会沉积在邻近晶片顶表面的通孔的侧壁上。导体（810）电镀到通孔中。在另一个实施例中，通过干膜抗蚀剂掩模（1110）将种子沉积在晶片的开口中。干膜抗蚀剂突出于开口的边缘，因此种子不会沉积在邻近晶片顶表面的开口的侧壁上。在另一个实施例中，电介质（120）通过非接触式物理气相沉积（PVD）工艺在半导体衬底（110）的开口中形成，该方法将电介质沉积在侧壁上而不是开口的底部。通过化学镀在底部形成种子（610）。导体（810）电镀在种子上。在另一个实施例中，电介质（2910）形成在开口中以覆盖开口的整个表面。非共形层（120）通过PVD沉积在侧壁上而不是开口的底部。用非保形层（120）作为掩模将电介质（2910）从底部蚀刻掉。通过化学镀在底部形成种子（610）。非保形层可以通过电镀形成。可以通过电镀沉积钽，然后阳极氧化。还提供了其他实施例。

2. 发明授权

US06749764B1 Plasma processing comprising three rotational motions of an article being processed 失效
标题翻译：等离子体处理包括被处理物品的三个旋转运动
公开(公告)号：US06749764B1
公开(公告)日：2004-06-15
申请号：US09713137
申请日：2000-11-14
申请人： Oleg Siniaguine , Sergey Savastiouk , Patrick Halahan , Sam Kao
发明人： Oleg Siniaguine , Sergey Savastiouk , Patrick Halahan , Sam Kao
IPC分类号： B05C300
CPC分类号： H01J37/32761 , H01L21/6838
摘要： An article which is being processed with plasma is moved during plasma processing so that the motion of the article comprises at least a first rotational motion, a second rotational motion, and a third rotational motion which occur simultaneously. The apparatus that moves the article comprises a first arm rotatable around a first axis, a second arm rotatably attached to the first arm and rotating the article around a second axis, and a rotational mechanism for inducing a rotational motion of the article in addition to, and simultaneously with, the rotation of the first and second arms.
摘要翻译：正在等离子体处理的制品在等离子体处理期间移动，使得制品的运动包括同时发生的至少第一旋转运动，第二旋转运动和第三旋转运动。移动物品的装置包括可围绕第一轴线旋转的第一臂，可旋转地附接到第一臂并使制品围绕第二轴线旋转的第二臂，以及用于引起物品的旋转运动的旋转机构，并且同时具有第一和第二臂的旋转。

3. 发明申请

US20050170647A1 Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby 审中-公开
公开(公告)号：US20050170647A1
公开(公告)日：2005-08-04
申请号：US11055940
申请日：2005-02-10
申请人： Patrick Halahan , Sam Kao , Bosco Lan , Sergey Savastiouk , Oleg Siniaguine
发明人： Patrick Halahan , Sam Kao , Bosco Lan , Sergey Savastiouk , Oleg Siniaguine
IPC分类号： H01L21/768 , H01L23/48 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76873 , H01L21/76874 , H01L21/76898 , H01L23/481 , H01L23/53238 , H01L2924/0002 , Y10S438/977 , H01L2924/00012 , H01L2924/00
摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

4. 发明授权

US06448153B2 Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners 有权
标题翻译：使用干蚀刻对半导体晶片进行薄化和切割，并获得具有圆形底部边缘和拐角的半导体芯片
公开(公告)号：US06448153B2
公开(公告)日：2002-09-10
申请号：US09752802
申请日：2000-12-28
申请人： Oleg Siniaguine , Patrick Halahan , Sergey Savastiouk
发明人： Oleg Siniaguine , Patrick Halahan , Sergey Savastiouk
IPC分类号： H01L21301
CPC分类号： H01L25/50 , H01L21/76898 , H01L21/78 , H01L23/481 , H01L23/482 , H01L25/0657 , H01L29/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/014 , H01L2924/10158 , H01L2924/14
摘要： A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then, the wafer is placed into a non-contact wafer holder, and the wafer backside is blanket etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip's backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips' bottom edges and coners. As a result, the chip becomes more reliable, and in particular more resistant to thermal and other stresses.
摘要翻译：在变薄之前切割半导体晶片。晶片仅被部分通过切割，以形成至少与从晶片获得的每个芯片的最终厚度相同的凹槽。然后，将晶片放置在非接触晶片保持器中，并且用干蚀刻（例如，大气压等离子体蚀刻）对晶片背面进行全面蚀刻。将晶片减薄直到凹槽从背面露出。干蚀刻使芯片的背面光滑。在凹槽已经暴露之后，继续进行干法蚀刻以去除芯片侧壁的破坏并绕过芯片的底部边缘和锥体。结果，芯片变得更可靠，特别是更耐热和其它应力。

5. 发明授权

US06897148B2 Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby 有权
标题翻译：导电材料的电镀和化学镀电镀到开口中，由此得到的结构
公开(公告)号：US06897148B2
公开(公告)日：2005-05-24
申请号：US10410929
申请日：2003-04-09
申请人： Patrick A. Halahan , Sam Kao , Bosco Lan , Sergey Savastiouk , Oleg Siniaguine
发明人： Patrick A. Halahan , Sam Kao , Bosco Lan , Sergey Savastiouk , Oleg Siniaguine
IPC分类号： H01L21/768 , H01L23/48 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76873 , H01L21/76874 , H01L21/76898 , H01L23/481 , H01L23/53238 , H01L2924/0002 , Y10S438/977 , H01L2924/00012 , H01L2924/00
摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.
摘要翻译：在包括半导体衬底（110）的晶片（104）中形成通孔（114）。种子层（610）溅射在晶片的底表面上。种子不会沉积在邻近晶片顶表面的通孔的侧壁上。导体（810）电镀到通孔中。在另一个实施例中，通过干膜抗蚀剂掩模（1110）将种子沉积在晶片的开口中。干膜抗蚀剂突出于开口的边缘，因此种子不会沉积在邻近晶片顶表面的开口的侧壁上。在另一个实施例中，电介质（120）通过非接触式物理气相沉积（PVD）工艺在半导体衬底（110）的开口中形成，该方法将电介质沉积在侧壁上而不是开口的底部。通过化学镀在底部形成种子（610）。导体（810）电镀在种子上。在另一个实施例中，电介质（2910）形成在开口中以覆盖开口的整个表面。非共形层（120）通过PVD沉积在侧壁上而不是开口的底部。用非保形层（120）作为掩模将电介质（2910）从底部蚀刻掉。通过化学镀在底部形成种子（610）。非保形层可以通过电镀形成。可以通过电镀沉积钽，然后阳极氧化。还提供了其他实施例。

6. 发明授权

US07521360B2 Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby 有权
标题翻译：导电材料的电镀和化学镀电镀到开口中，由此得到的结构
公开(公告)号：US07521360B2
公开(公告)日：2009-04-21
申请号：US11548053
申请日：2006-10-10
申请人： Patrick A. Halahan , Sam Kao , Bosco Lan , Sergey Savastiouk , Oleg Siniaguine
发明人： Patrick A. Halahan , Sam Kao , Bosco Lan , Sergey Savastiouk , Oleg Siniaguine
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76855 , H01L21/76873 , H01L21/76874 , H01L21/76898 , H01L23/481 , H01L23/53238 , H01L2924/0002 , Y10S438/977 , H01L2924/00012 , H01L2924/00
摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.
摘要翻译：在包括半导体衬底（110）的晶片（104）中形成通孔（114）。种子层（610）溅射在晶片的底表面上。种子不会沉积在邻近晶片顶表面的通孔的侧壁上。导体（810）电镀到通孔中。在另一个实施例中，通过干膜抗蚀剂掩模（1110）将种子沉积在晶片的开口中。干膜抗蚀剂突出于开口的边缘，因此种子不会沉积在邻近晶片顶表面的开口的侧壁上。在另一个实施例中，电介质（120）通过非接触式物理气相沉积（PVD）工艺在半导体衬底（110）的开口中形成，该方法将电介质沉积在侧壁上而不是开口的底部。通过化学镀在底部形成种子（610）。导体（810）电镀在种子上。在另一个实施例中，电介质（2910）形成在开口中以覆盖开口的整个表面。非共形层（120）通过PVD沉积在侧壁上而不是开口的底部。用非保形层（120）作为掩模将电介质（2910）从底部蚀刻掉。通过化学镀在底部形成种子（610）。非保形层可以通过电镀形成。可以通过电镀沉积钽，然后阳极氧化。还提供了其他实施例。

7. 发明授权

US06203661B1 Brim and gas escape for non-contact wafer holder 失效
标题翻译：用于非接触式晶片座的边缘和气体逸出
公开(公告)号：US06203661B1
公开(公告)日：2001-03-20
申请号：US09457042
申请日：1999-12-07
申请人： Oleg Siniaguine , Sergey Savastiouk , Alex Berger
发明人： Oleg Siniaguine , Sergey Savastiouk , Alex Berger
IPC分类号： C23F102
CPC分类号： H01L21/67069 , H01J37/3244 , H01J37/32449
摘要： The present invention comprises a brim surrounding a wafer or wafer-like object during plasma etching in a non-contact wafer holder, such brim facilitating uniform flow of the plasma discharge around the edge of the wafer during plasma etching. The brim of the present invention avoids plasma instability and non-uniform flow typical of conventional plasma etching near the edges of the wafer being etched. The brim of the present invention, by facilitating uniform and stable plasma flows, decreases non-uniform etching. One embodiment of the present invention permits the brim to move in the axial direction from a position substantially. This permits the etching process to be controlled for more uniform and precise wafer etching as lowering the brim tends to shadow the edge region of the wafer from the plasma, reducing etching in the edge region while not significantly affecting etching in the central regions of the wafer. Another embodiment of the wafer includes a barrier on the upper side of the brim directed upward from the brim at an oblique angle away from the wafer. This barrier contacts the upper surface of the brim so as to leave a protrusion or debris-collecting shelf on the upper interior portion of the brim. This shelf in combination with the upward oblique barrier deflects the plasma and debris from plasma etching away from the wafer. Another embodiment of the invention includes a gas-controlling baffle in which gas flow around the edge of the wafer may be controlled to compensate for mechanical imprecision in the gap between the brim and the wafer and/or to provide an additional means of controlling etching in the vicinity of the edge of the wafer.
摘要翻译：本发明包括在非接触晶片保持器中的等离子体蚀刻期间围绕晶片或晶片状物体的边缘，这样的边缘有助于等离子体蚀刻期间围绕晶片边缘的等离子体放电的均匀流动。本发明的边缘避免了正在蚀刻的晶片的边缘附近的常规等离子体蚀刻的等离子体不稳定性和不均匀流动。通过促进均匀和稳定的等离子体流动，本发明的边缘减少了不均匀的蚀刻。本发明的一个实施例允许边缘在大体上从轴线方向移动。这允许蚀刻过程被控制以更均匀和精确的晶片蚀刻，因为降低边缘倾向于从等离子体遮蔽晶片的边缘区域，减少边缘区域中的蚀刻，同时不显着影响晶片的中心区域中的蚀刻。晶片的另一实施例包括位于边缘上侧的阻挡物，其从棱边向上以与倾斜角度相离的晶片向上指向。该阻挡件接触边缘的上表面，以便在边缘的上部内部部分留下突起或碎屑收集架。这个搁板与向上的倾斜屏障组合使得等离子体和碎屑等离子体蚀刻偏离晶片。本发明的另一实施例包括气体控制挡板，其中围绕晶片边缘的气流可被控制以补偿边缘和晶片之间的间隙中的机械不精确性和/或提供控制蚀刻的附加装置晶片边缘附近。

8. 发明授权

US06667242B2 Brim and gas escape for non-contact wafer holder 有权
标题翻译：用于非接触式晶片座的边缘和气体逸出
公开(公告)号：US06667242B2
公开(公告)日：2003-12-23
申请号：US09757242
申请日：2001-01-08
申请人： Oleg Siniaguine , Sergey Savastiouk , Alex Berger
发明人： Oleg Siniaguine , Sergey Savastiouk , Alex Berger
IPC分类号： C23F102
CPC分类号： H01L21/67069 , H01J37/3244 , H01J37/32449
摘要： The present invention comprises a brim surrounding a wafer or wafer-like object during plasma etching in a non-contact wafer holder, such brim facilitating uniform flow of the plasma discharge around the edge of the wafer during plasma etching. The brim of the present invention avoids plasma instability and non-uniform flow typical of conventional plasma etching near the edges of the wafer being etched. The brim of the present invention, by facilitating uniform and stable plasma flows, decreases non-uniform etching. One embodiment of the present invention permits the brim to move in the axial direction from a position substantially. This permits the etching process to be controlled for more uniform and precise wafer etching as lowering the brim tends to shadow the edge region of the wafer from the plasma, reducing etching in the edge region while not significantly affecting etching in the central regions of the wafer. Another embodiment of the wafer includes a barrier on the upper side of the brim directed upward from the brim at an oblique angle away from the wafer. This barrier contacts the upper surface of the brim so as to leave a protrusion or debris-collecting shelf on the upper interior portion of the brim. This shelf in combination with the upward oblique barrier deflects the plasma and debris from plasma etching away from the wafer. Another embodiment of the invention includes a gas-controlling baffle in which gas flow around the edge of the wafer may be controlled to compensate for mechanical imprecision in the gap between the brim and the wafer and/or to provide an additional means of controlling etching in the vicinity of the edge of the wafer.
摘要翻译：本发明包括在非接触晶片保持器中的等离子体蚀刻期间围绕晶片或晶片状物体的边缘，这样的边缘有助于等离子体蚀刻期间围绕晶片边缘的等离子体放电的均匀流动。本发明的边缘避免了正在蚀刻的晶片的边缘附近的常规等离子体蚀刻的等离子体不稳定性和不均匀流动。通过促进均匀和稳定的等离子体流动，本发明的边缘减少了不均匀的蚀刻。本发明的一个实施例允许边缘在大体上从轴线方向移动。这允许蚀刻过程被控制以更均匀和精确的晶片蚀刻，因为降低边缘倾向于从等离子体遮蔽晶片的边缘区域，减少边缘区域中的蚀刻，同时不显着影响晶片的中心区域中的蚀刻。晶片的另一实施例包括位于边缘上侧的阻挡物，其从棱边向上以与倾斜角度相离的晶片向上指向。该阻挡件接触边缘的上表面，以便在边缘的上部内部部分留下突起或碎屑收集架。这个搁板与向上的倾斜屏障组合使得等离子体和碎屑等离子体蚀刻偏离晶片。本发明的另一实施例包括气体控制挡板，其中围绕晶片边缘的气流可被控制以补偿边缘和晶片之间的间隙中的机械不精确性和/或提供控制蚀刻的附加装置晶片边缘附近。

9. 发明授权

US06498074B2 Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners 有权
标题翻译：使用干蚀刻对半导体晶片进行薄化和切割，并获得具有圆形底部边缘和拐角的半导体芯片
公开(公告)号：US06498074B2
公开(公告)日：2002-12-24
申请号：US09876888
申请日：2001-06-06
申请人： Oleg Siniaguine , Patrick B. Halahan , Sergey Savastiouk
发明人： Oleg Siniaguine , Patrick B. Halahan , Sergey Savastiouk
IPC分类号： H01L2146
CPC分类号： H01L24/96 , H01L21/304 , H01L21/3065 , H01L21/441 , H01L21/76898 , H01L21/78 , H01L23/481 , H01L23/482 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L29/0657 , H01L2224/16 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/00014 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01072 , H01L2924/014 , H01L2924/10158 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , Y10S438/977 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then the wafer backside is etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip's backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips' bottom edges and corners. The grooves' aspect ratio is large to reduce the lateral etch rate of the chip sidewalls and thus allow more area for on-chip circuitry.
摘要翻译：在变薄之前切割半导体晶片。晶片仅被部分通过切割，以形成至少与从晶片获得的每个芯片的最终厚度相同的凹槽。然后用干蚀刻蚀刻晶片背面，例如大气压等离子体蚀刻。将晶片减薄直到凹槽从背面露出。干蚀刻使芯片的背面光滑。在凹槽已经暴露之后，继续进行干蚀刻以去除来自芯片侧壁的损伤并围绕芯片的底部边缘和角落。凹槽的纵横比很大，以减小芯片侧壁的横向蚀刻速率，从而允许更多的片上电路面积。

10. 发明授权

US06402843B1 Non-contact workpiece holder 失效
标题翻译：非接触式工件支架
公开(公告)号：US06402843B1
公开(公告)日：2002-06-11
申请号：US09456135
申请日：1999-12-07
申请人： Oleg Siniaguine , Sergey Savastiouk , Alex Berger , Igor Bagriy
发明人： Oleg Siniaguine , Sergey Savastiouk , Alex Berger , Igor Bagriy
IPC分类号： C23C1600
CPC分类号： H01L21/68735 , B25B11/005 , B65G47/911 , H01L21/6838
摘要： The present invention relates to a non-contact holder for substantially planar workpieces, particularly suited for holding thin workpieces without substantial distortion. The present invention includes a cylindrical chuck having a gas inlet orifice positioned at an oblique. The introduction of pressurized gas creates a vortex and vacuum attraction holding a wafer in close proximity to the chuck while the gas exiting from the chuck prevents contact between wafer and chuck. Small diameter chucks located in close proximity help the present invention avoid distortion when processing very thin workpieces. The gas exiting from the chuck of the present invention exits preferentially in a certain angular direction. Chucks are arranged on the wafer holder such that exiting gas is preferentially directed radially towards the periphery of the holder and that exiting gas is directed between adjacent chucks, not directly at another nearby chuck. Chucks on the periphery of the holder are positioned have the gas exiting therefrom towards the periphery of the holder and overlapping the gas flow from immediately adjacent chucks. Chucks on the periphery of the holder are located as close together as feasible. The combination of overlapping gas flow and close proximity creates a gas shield on the boundary of the wafer holder.
摘要翻译：本发明涉及一种用于基本上平面的工件的非接触保持器，特别适用于保持薄的工件而没有实质的变形。本发明包括具有位于倾斜处的气体入口孔的圆柱形卡盘。加压气体的引入产生涡流和真空吸引，将晶片保持在靠近卡盘的位置，而从卡盘排出的气体防止晶片和卡盘之间的接触。紧邻的小直径卡盘有助于本发明在加工非常薄的工件时避免扭曲。从本发明的卡盘排出的气体优先在一定的角度方向上离开。卡盘布置在晶片保持器上，使得离开的气体优选地朝向保持器的周边径向引导，并且排出气体被引导在相邻卡盘之间，而不是直接在另一个附近卡盘处。定位在保持器周边的卡盘具有从其朝向保持器的周边离开的气体，并与来自紧邻的卡盘的气流重叠。夹持器外围的夹头尽可能靠近在一起。重叠气流和近距离的组合在晶片保持器的边界上形成气体屏蔽。

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