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1. 发明申请

US20210311349A1 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, DISPLAY PANEL AND DISPLAY DEVICE 有权
公开(公告)号：US20210311349A1
公开(公告)日：2021-10-07
申请号：US16319617
申请日：2018-06-05
申请人： ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. , BOE TECHNOLOGY GROUP CO., LTD.
发明人： Yang XIE , Weixin MENG , Jian GUO
IPC分类号： G02F1/1333 , H01L27/32 , H01L51/52 , H01L51/56 , G02F1/1337 , G02F1/1362 , G02F1/1335
摘要： An array substrate, a manufacturing method of the same, a display panel and a display device are provided. The array substrate includes a display region and a peripheral region around the display region, a photosensitive layer is in the display region and a peripheral circuit is in the peripheral region. The array substrate further includes an alignment film covering the photosensitive layer and the peripheral circuit. The array substrate further includes an insulating layer between the peripheral circuit and the alignment film. The alignment film is a photo alignment film, and the insulating layer is configured to absorb and/or reflect an alignment light adopted for performing photoalignment to obtain the alignment film.

2. 发明申请

US20190049765A1 LIQUID CRYSTAL DRIPPING NOZZLE, LIQUID CRYSTAL DRIPPING DEVICE AND METHOD FOR DRIPPING LIQUID CRYSTAL 审中-公开
公开(公告)号：US20190049765A1
公开(公告)日：2019-02-14
申请号：US16019036
申请日：2018-06-26
申请人： BOE TECHNOLOGY GROUP CO., LTD. , ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
发明人： Shuaimin JIAN , Weixin MENG , Jian GUO , Lubiao SUN , Wei ZHENG , Yanzhao PENG
IPC分类号： G02F1/1341 , G02F1/13 , B05C5/02
摘要： A liquid crystal dripping nozzle, a liquid crystal dripping device, and a method of dripping liquid crystal are provided. The liquid crystal dripping nozzle includes: a carrier; a main dripping nozzle, disposed in a central region of the carrier and configured for dripping liquid crystal; and a plurality of auxiliary dripping nozzles, disposed in a corner region of the carrier and configured for dripping liquid crystal, wherein the plurality of auxiliary dripping nozzles are arranged around the main dripping nozzle.

3. 发明申请

US20160043117A1 ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE 有权
标题翻译：阵列基板及其制造方法及显示装置
公开(公告)号：US20160043117A1
公开(公告)日：2016-02-11
申请号：US14429961
申请日：2014-07-21
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Jian GUO
IPC分类号： H01L27/12
CPC分类号： H01L27/1288 , G02F1/1368 , G02F2201/121 , G02F2201/123 , G02F2201/124 , H01L27/124 , H01L27/3276
摘要： Embodiments of the present disclosure provide an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate includes: forming a gate metal layer, a gate insulating layer, an active layer and a source-drain metal layer on a base substrate. The forming the gate insulating layer, the active layer and the source-drain metal layer on the base substrate comprises: forming a gate insulating film, an active layer film and a source-drain metal film on the base substrate; forming the gate insulating layer, the active layer and the source-drain metal layer by a single patterning process. The number of the exposing process is reduced, the production cycle is shortened and the fabrication cost is reduced.
摘要翻译：本公开的实施例提供阵列基板及其制造方法以及显示装置。阵列基板的制造方法包括：在基底基板上形成栅极金属层，栅极绝缘层，有源层和源极 - 漏极金属层。在基底基板上形成栅极绝缘层，有源层和源极 - 漏极金属层包括：在基底基板上形成栅极绝缘膜，有源层膜和源极 - 漏极金属膜; 通过单个图案化工艺形成栅极绝缘层，有源层和源极 - 漏极金属层。曝光过程的数量减少，生产周期缩短，制造成本降低。

4. 发明申请

US20160013294A1 MANUFACTURING METHOD OF THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR 有权
标题翻译：薄膜晶体管和薄膜晶体管的制造方法
公开(公告)号：US20160013294A1
公开(公告)日：2016-01-14
申请号：US14425994
申请日：2014-06-26
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Xuecheng HOU , Tao WU , Jian GUO
IPC分类号： H01L29/66 , H01L29/417 , H01L21/308 , H01L29/786 , H01L21/3213
CPC分类号： H01L29/66765 , H01L21/3081 , H01L21/3083 , H01L21/32139 , H01L27/1288 , H01L29/41733 , H01L29/66969 , H01L29/78669 , H01L29/78678 , H01L29/7869
摘要： A manufacturing method of a thin film transistor and a thin film transistor are provided. In the manufacturing method, formation of pattern of a source electrode (7), a drain electrode (8) and an active layer (6) comprises: forming a semiconductor layer (10) and a conductive layer (11) that cover the whole substrate on the substrate in sequence; forming a first photoresist layer (4) at a region where the source electrode is to be formed and at a region where the drain electrode is to be formed on the conductive layer (11), respectively; forming a second photoresist layer (5) at least at a gap between the source electrode and the drain electrode that are to be formed on the conductive layer (11); conducting an etching process on the substrate with the first photoresist layer (4), the second photoresist layer (5), the semiconductor layer (10) and the conductive layer (11) formed thereon, so as to form pattern of the active layer (6), the source electrode (7) and the drain electrode (8).
摘要翻译：提供薄膜晶体管和薄膜晶体管的制造方法。在制造方法中，源电极（7），漏电极（8）和有源层（6）的图案的形成包括：形成覆盖整个基板的半导体层（10）和导电层（11）在底物上; 在要形成源电极的区域和在导电层（11）上分别形成漏电极的区域上形成第一光致抗蚀剂层（4）; 在所述导电层（11）上形成至少在所述源电极和所述漏电极之间的间隙处形成第二光致抗蚀剂层（5）; 在所述基板上对所述第一光致抗蚀剂层（4），所述第二光致抗蚀剂层（5），所述半导体层（10）和所述导电层（11）进行蚀刻处理，以形成所述有源层的图案（ 6），源电极（7）和漏电极（8）。

5. 发明申请

US20150336129A1 MASK 有权
标题翻译：面具
公开(公告)号：US20150336129A1
公开(公告)日：2015-11-26
申请号：US14546237
申请日：2014-11-18
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Jian GUO
IPC分类号： B05C21/00
CPC分类号： B05C21/005 , G03F1/42 , G03F1/44 , G03F1/70 , H01L21/308 , H01L2224/10135
摘要： The present invention provides a mask, on which a preset pattern is provided. First test patterns for determining an amount of a position offset of the mask during its movement are provided on the mask at a first side of the preset pattern and a second side of the preset pattern opposite to the first side, respectively. When being moved in a direction from the first side to the second side by a standard distance, the mask can determine whether a position offset occurs to the mask during its movement, and determine an amount of the position offset if a position offset occurs. Thus, the position offset of the mask can be corrected, thereby obtaining an accurate predetermined pattern on a glass substrate.
摘要翻译：本发明提供了一种掩模，其上设有预设图案。用于确定掩模在其移动期间的位置偏移的量的第一测试图案分别在预设图案的第一侧和与第一侧相对的预设图案的第二侧处设置在掩模上。当沿着从第一侧到第二侧的方向移动标准距离时，掩模可以确定在其移动期间是否发生位置偏移到掩模，并且如果发生位置偏移，则确定位置偏移的量。因此，可以校正掩模的位置偏移，从而在玻璃基板上获得准确的预定图案。

6. 发明申请

US20150333182A1 METHOD OF FABRICATING ARRAY SUBSTRATE, ARRAY SUBSTRATE, AND DISPLAY DEVICE 审中-公开
标题翻译：制造阵列基板，阵列基板和显示装置的方法
公开(公告)号：US20150333182A1
公开(公告)日：2015-11-19
申请号：US14516882
申请日：2014-10-17
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Jian GUO
IPC分类号： H01L29/786 , H01L29/66 , H01L21/467 , H01L27/12 , H01L21/4757 , H01L21/475 , H01L29/24 , H01L21/02
CPC分类号： H01L27/1288 , H01L21/02565 , H01L21/467 , H01L21/475 , H01L21/47573 , H01L27/1225 , H01L27/124 , H01L27/1259 , H01L29/24 , H01L29/66969 , H01L29/7869
摘要： The embodiments of the present invention provide a method of fabricating an array substrate, including steps of funning a thin film transistor, a pixel electrode and a common electrode line, wherein the step of forming the thin film transistor includes steps of forming patterns of a gate, a gate insulation layer, a semiconductor layer, an etch stop layer, a source and a drain, and the gate and the common electrode line are formed in the same layer. In the method, a gate insulation film and a semiconductor film are sequentially formed, and a pattern including the semiconductor layer is formed by one patterning process; and then an etch stop film is formed, and as pattern including the gate insulation layer and the etch stop layer is formed by one patterning process.
摘要翻译：本发明的实施例提供一种制造阵列基板的方法，包括使薄膜晶体管，像素电极和公共电极线起作用的步骤，其中形成薄膜晶体管的步骤包括形成栅极图案的步骤栅极绝缘层，半导体层，蚀刻停止层，源极和漏极以及栅极和公共电极线形成在同一层中。在该方法中，顺序地形成栅极绝缘膜和半导体膜，并且通过一个图案化工艺形成包括半导体层的图案; 然后形成蚀刻停止膜，并且通过一个图案化工艺形成包括栅极绝缘层和蚀刻停止层的图案。

7. 发明申请

US20150325591A1 ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF AS WELL AS DISPLAY PANEL 有权
标题翻译：阵列基板和制造方法以及显示面板
公开(公告)号：US20150325591A1
公开(公告)日：2015-11-12
申请号：US14387885
申请日：2013-12-09
申请人： BOE Technology Group Co., Ltd. , Beijing BOE Optoelectronics Technology Co., Ltd.
发明人： Jian GUO
IPC分类号： H01L27/12 , H01L21/3065 , H01L21/311
CPC分类号： H01L27/124 , G02F1/13394 , H01L21/3065 , H01L21/31116 , H01L21/32136 , H01L27/1259
摘要： An array substrate and a manufacturing method thereof as well as a display panel are provided. The manufacturing method comprises: forming a pattern including a scanning line (32) and a spacer base (33) on a same layer of a substrate (31); forming a gate insulating layer (34); forming a pattern including an active layer (35), a data line, a source electrode and a drain electrode; forming a passivation layer (36); sequentially etching the passivation layer (36) and the gate insulating layer (34) through a dry etching method to form a via hole (38) exposing the spacer base (33), and inducing materials generated from an etching process in a reaction cavity to deposit on a surface of the spacer base (33) through an electric field formed by the spacer base (33) exposed in the via hole (38) and etching gas adopted in the etching process, to form a spacer (39).
摘要翻译：提供阵列基板及其制造方法以及显示面板。该制造方法包括：在基板（31）的同一层上形成包括扫描线（32）和间隔基座（33）的图案; 形成栅极绝缘层（34）; 形成包括有源层（35），数据线，源电极和漏电极的图案; 形成钝化层（36）; 通过干法蚀刻方法依次蚀刻钝化层（36）和栅极绝缘层（34），以形成暴露间隔体基体（33）的通孔（38），并且将从反应腔中的蚀刻工艺产生的材料诱导到通过由在通孔（38）中露出的间隔体基体（33）形成的电场和蚀刻工序中所采用的蚀刻气体，在间隔基体（33）的表面上沉积，形成间隔物（39）。

8. 发明申请

US20150318313A1 ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE 审中-公开
标题翻译：阵列基板及其制造方法，显示装置
公开(公告)号：US20150318313A1
公开(公告)日：2015-11-05
申请号：US14405008
申请日：2013-11-20
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Tiansheng LI , Jian GUO , Zhenyu XIE
IPC分类号： H01L27/12 , H01L27/15
CPC分类号： H01L27/1251 , H01L27/124 , H01L27/127 , H01L27/1288 , H01L27/15
摘要： An array substrate, comprising a display region and a GOA region. In the GOA region, a gate metal electrode, a gate insulating layer, an active layer, a transition layer, and a source-drain metal electrode are formed in sequence from bottom to top, and a via hole is provided penetrating the transition layer, the active layer and the gate insulating layer, the source-drain metal electrode is electrically connected to the gate metal electrode through the via hole; and at an edge of the via hole, there is formed an angle opening upward at edges of the transition layer and the active layer. There are further disclosed a manufacturing method of the array substrate and a display device provided with the array substrate.
摘要翻译：阵列基板，包括显示区域和GOA区域。在GOA区域中，从底部到顶部依次形成栅极金属电极，栅极绝缘层，有源层，过渡层和源极 - 漏极金属电极，并且穿过过渡层的通孔，有源层和栅极绝缘层，源极 - 漏极金属电极通过通孔电连接到栅极金属电极; 并且在通孔的边缘处，在过渡层和有源层的边缘处形成向上开口的角度。还公开了阵列基板的制造方法和设置有阵列基板的显示装置。

9. 发明申请

US20150279875A1 ARRAY SUBSTRATE AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE 有权
标题翻译：阵列基板及其制备方法和显示装置
公开(公告)号：US20150279875A1
公开(公告)日：2015-10-01
申请号：US14492709
申请日：2014-09-22
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Jian GUO
IPC分类号： H01L27/12
CPC分类号： H01L27/1288 , H01L27/124
摘要： The invention relates to an array substrate and a method for preparing the same, and a display device. The method for preparing an array substrate comprises steps S1) forming a pattern, which includes a gate electrode, a gate electrode insulating layer, an active layer and a source-drain electrode, on a base substrate; and S2) forming a transparent conducting layer on the base substrate on which step S1 has been accomplished, and simultaneously forming a pattern including a pixel electrode and a data line via a one-time patterning process. In this method, the steps of the manufacture process can be reduced, the production cost can be saved, and the production efficiency can be improved. Moreover, since the pixel electrode and the data line may be both formed to have a low resistance value and a high light transmission rate, the performance of the array substrate can be improved.
摘要翻译：本发明涉及阵列基板及其制备方法以及显示装置。制备阵列基板的方法包括步骤S1）在基底基板上形成包括栅电极，栅电极绝缘层，有源层和源漏电极的图案; 和S2）在已经完成了步骤S1的基底基板上形成透明导电层，并且通过一次构图工艺同时形成包括像素电极和数据线的图案。在该方法中，可以降低制造工序的工序，节省生产成本，提高生产效率。此外，由于像素电极和数据线都可以形成为具有低电阻值和高透光率，因此可以提高阵列基板的性能。

10. 发明申请

US20160380005A1 ARRAY SUBSTRATE, PREPARATION METHOD THEREOF AND DISPLAY DEVICE 有权
标题翻译：阵列基板，其制备方法和显示装置
公开(公告)号：US20160380005A1
公开(公告)日：2016-12-29
申请号：US15098914
申请日：2016-04-14
申请人： BOE TECHNOLOGY GROUP CO., LTD. , BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
发明人： Xuecheng HOU , Kai LU , Jian GUO
IPC分类号： H01L27/12
CPC分类号： H01L27/1248 , H01L27/124 , H01L27/1244 , H01L27/1259
摘要： The present invention provides an array substrate, a preparation method thereof and a display device. The array substrate includes at least one thin film transistor and a resin layer having at least one resin via hole, wherein a film-thickness-difference-adjusting layer used for reducing the film thickness difference at the resin via hole is arranged at the lower part of the resin layer in at least a part of the resin via hole. By providing the film-thickness-difference-adjusting layer, the film thickness difference at the resin via hole can be effectively reduced, and when a photolithographic process is performed, the difference of the thickness of the photoresist here and the thicknesses at other positions is reduced, so that the via hole fluctuation of a passivation layer caused by the larger film thickness difference at the resin via hole is improved, and the metal residue problem of the pixel electrodes is effectively avoided.
摘要翻译：本发明提供阵列基板，其制备方法和显示装置。阵列基板包括至少一个薄膜晶体管和具有至少一个树脂通孔的树脂层，其中用于降低树脂通孔的膜厚差的膜厚度差调节层设置在下部在树脂通孔的至少一部分中的树脂层。通过设置薄膜厚度差调节层，可以有效地降低树脂通孔的膜厚差，当进行光刻处理时，这里的光致抗蚀剂的厚度差和其他位置的厚度之差为从而提高了由树脂通孔中较大的膜厚度差引起的钝化层的通孔波动，有效地避免了像素电极的金属残留问题。

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