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1. 发明授权

US06317803B1 High-throughput interconnect having pipelined and non-pipelined bus transaction modes 失效
标题翻译：具有流水线和非流水线总线事务模式的高吞吐量互连
公开(公告)号：US06317803B1
公开(公告)日：2001-11-13
申请号：US08721893
申请日：1996-09-27
申请人： Norman J. Rasmussen , Gary A. Solomon , David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case
发明人： Norman J. Rasmussen , Gary A. Solomon , David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case
IPC分类号： G06F1300
CPC分类号： G06F13/1615 , G06F13/161 , G06F13/1631
摘要： A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.
摘要翻译：提供了高吞吐量的存储器访问端口。该端口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。该端口允许内存读取和写入请求流水线，以隐藏内存访问延迟的影响。特别地，端口允许以非流水线模式（例如由PCI提供）或以流水线模式执行总线事务。在流水线模式中，允许在第一存储器访问请求和其对应的数据传送之间插入一个或多个附加存储器访问请求。相比之下，在非流水线模式下，不能在第一存储器访问请求和其对应的数据传输之间插入附加存储器访问请求。

2. 发明授权

US5911051A High-throughput interconnect allowing bus transactions based on partial access requests 失效
标题翻译：高吞吐量互连允许基于部分访问请求的总线事务
公开(公告)号：US5911051A
公开(公告)日：1999-06-08
申请号：US721686
申请日：1996-09-27
申请人： David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case , Kim A. Meinerth , Brian K. Langendorf
发明人： David G. Carson , George R. Hayek , Brent S. Baxter , Colyn Case , Kim A. Meinerth , Brian K. Langendorf
IPC分类号： G06F13/16 , G06F13/14
CPC分类号： G06F13/1631 , G06F13/161 , G06F13/1615
摘要： A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target. If such segment or segments have changed since the previous access request, then they are provided to the target only for purposes of updating state in the target. Access requests may optionally be provided to the target on a separate port from the port used to transmit data in response to access requests.
摘要翻译：提供了高吞吐量的存储器访问接口。该接口包括在系统内存和视频/图形或音频适配器之间提供比使用标准本地总线架构（如PCI或ISA）可能提供更高数据传输速率的功能。该接口允许以这样的方式执行存储器访问请求，使得只有访问请求的一部分需要被发送到目标设备以用于某些总线事务。每个访问请求包括命令位，地址位和长度位。在发起设备中，每个访问请求被分成三个段，它们存储在起始设备和目标设备中的单独的寄存器中。目标设备只需要包含最低位地址位和长度位的段来启动总线事务。因此，如果其他两个段中的任何一个从先前的访问请求起没有改变，则这样的段或段不被发送到目标。如果这些片段或片段自从先前的访问请求以来已经改变，那么它们被提供给目标，仅用于更新目标中的状态。访问请求可以可选地在与用于响应于访问请求传输数据的端口的单独端口上提供给目标。

3. 发明授权

US07382373B2 Method and apparatus for producing animation 有权
标题翻译：制作动画的方法和装置
公开(公告)号：US07382373B2
公开(公告)日：2008-06-03
申请号：US10741808
申请日：2003-12-19
申请人： Brent S. Baxter , Paul M. Brown , William H. Clifford
发明人： Brent S. Baxter , Paul M. Brown , William H. Clifford
IPC分类号： G06T13/00
CPC分类号： G06T15/04 , G06T13/80
摘要： In some embodiments, a method includes generating blurred copies of an object by applying multi-texturing to the object during one pass through a graphics processing pipeline. In some embodiments, a graphics pipeline includes a texture memory and a graphics processor coupled to the texture memory. The texture memory provides a location to store texture information. The graphics processor provides processor to process the texture information by shifting and blending the texture information in one pass through the graphics processor to obtain shifted and blended texture information.
摘要翻译：在一些实施例中，一种方法包括通过在通过图形处理管线的一次通过期间对对象应用多纹理来生成对象的模糊副本。在一些实施例中，图形管线包括纹理存储器和耦合到纹理存储器的图形处理器。纹理记忆库提供了存储纹理信息的位置。图形处理器通过在一次通过图形处理器中移动和混合纹理信息来提供处理器来处理纹理信息，以获得移位和混合纹理信息。

4. 发明授权

US07158532B2 Half duplex link with isochronous and asynchronous arbitration 失效
标题翻译：具有同步和异步仲裁的半双工链路
公开(公告)号：US07158532B2
公开(公告)日：2007-01-02
申请号：US09215559
申请日：1998-12-18
申请人： John I. Garney , Brent S. Baxter
发明人： John I. Garney , Brent S. Baxter
IPC分类号： H04L5/16
CPC分类号： H04L12/40058 , H04L12/40084 , H04L12/6418
摘要： Transactions are scheduled over a half duplex link between a first device, such as an IO unit, and a second device, such as a memory controller. Information flowing over the half duplex link is divided into a plurality of service periods, and an isochronous transaction, such as an isochronous memory read or write, is scheduled in a service period N if the isochronous transaction is ready to be serviced before service period N at the first or second device. An asynchronous transaction ready to be serviced at the first or second device, such as an asynchronous memory read or write, is scheduled if no isochronous transaction is ready to be serviced. The asynchronous transaction may be scheduled by (a) scheduling an asynchronous transaction ready to be serviced at the first device if no asynchronous transaction is ready to be serviced at the second device; (b) scheduling an asynchronous transaction ready to be serviced at the second device if no asynchronous transaction is ready to be serviced at the first device; and (c) scheduling an asynchronous transaction ready to be serviced at the first or second device, according to an arbitration algorithm, if asynchronous transactions are ready to be serviced at both the first device and the second device. The amount of buffer space available in the first or second device may also be used to schedule asynchronous transactions.
摘要翻译：事务被安排在诸如IO单元的第一设备和诸如存储器控制器的第二设备之间的半双工链路上。在半双工链路上流动的信息被划分为多个服务周期，并且如果在服务周期N之前准备服务等时事务，则在服务周期N中调度诸如同步存储器读或写等同步事务在第一或第二设备。如果没有等时事务准备好服务，则调度在第一或第二设备上准备好服务的异步事务，例如异步存储器读或写。可以通过以下方式来调度异步事务：（a）如果没有异步事务准备好在第二设备处服务，则调度准备好在第一设备处服务的异步事务; （b）如果没有异步事务准备好在第一设备处被服务，则调度准备在第二设备处服务的异步事务; 以及（c）如果异步事务准备好在第一设备和第二设备两者处被服务，则根据仲裁算法来调度准备在第一或第二设备处服务的异步事务。第一或第二设备中可用的缓冲空间量也可用于调度异步事务。

5. 发明授权

US06477600B1 Apparatus and method for processing isochronous interrupts 有权
标题翻译：用于处理同步中断的装置和方法
公开(公告)号：US06477600B1
公开(公告)日：2002-11-05
申请号：US09327937
申请日：1999-06-08
申请人： Brent S. Baxter , John I. Garney
发明人： Brent S. Baxter , John I. Garney
IPC分类号： G06F1314
CPC分类号： G06F9/4825 , G06F13/24
摘要： A computer system provides for the use of isochronous interrupts by devices coupled with the system. Isochronous interrupt requests are received by an interrupt controller during a first time period, recorded, and executed during a second time period. The devices are equipped to handle the delay in interrupt execution. The interrupt controller is set to service isochronous interrupts on a periodic basis. The interrupt controller may flexibly schedule the execution of the isochronous interrupt request at any time during the second time period.
摘要翻译：计算机系统通过与系统耦合的设备提供同步中断的使用。同步中断请求在第一时间段期间由中断控制器接收，在第二时间段期间被记录和执行。这些设备配备了处理中断执行的延迟。中断控制器被设置为周期性地服务等时中断。中断控制器可以在第二时间段期间的任何时间灵活地安排同步中断请求的执行。

6. 发明授权

US06418538B1 Method and system for scheduling transactions over a half duplex link 有权
标题翻译：用于通过半双工链路调度事务的方法和系统
公开(公告)号：US06418538B1
公开(公告)日：2002-07-09
申请号：US09219321
申请日：1998-12-23
申请人： John I. Garney , Brent S. Baxter
发明人： John I. Garney , Brent S. Baxter
IPC分类号： G06F104
CPC分类号： G06F13/1605
摘要： Transactions are scheduled over a half duplex link between a first device and a second device. Information flowing over the half duplex link is divided into a plurality of service periods. According to one embodiment of the present invention, the transfer of a read request transaction, from the first device to the second device, is scheduled in one service period. The transfer of a write transaction, from the first device to the second device, is scheduled such that the write transaction will not be transferred across the half duplex link in the same service period as returning memory read data is transferred across the half duplex link. According to another embodiment of the present invention, a first transaction associated with a first agent is scheduled in a first service period according to a global schedule. The global schedule associates the first service period with the first agent. A second transaction associated with a second agent is scheduled in a second service period according to the global schedule. The global schedule associates the second service period with the second agent.
摘要翻译：交易被安排在第一设备和第二设备之间的半双工链路上。流经半双工链路的信息被分成多个服务周期。根据本发明的一个实施例，在一个服务周期内调度从第一设备到第二设备的读请求事务的传送。调度从第一设备到第二设备的写事务的传送，使得在返回的存储器读取数据通过半双工链路传输的同一服务周期内，写入事务将不在半双工链路上传输。根据本发明的另一实施例，与第一代理相关联的第一交易根据全局时间表在第一服务周期中被调度。全球时间表将第一个服务期与第一个代理相关联。与第二代理相关联的第二事务根据全局日程安排在第二服务周期中。全球时间表将第二个服务期与第二个代理相关联。

7. 发明授权

US06415367B1 Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme 有权
标题翻译：用于在基于时隙的存储器仲裁方案中减少异步服务延迟的装置
公开(公告)号：US06415367B1
公开(公告)日：2002-07-02
申请号：US09465527
申请日：1999-12-16
申请人： Brent S. Baxter , Stephen S. Pawlowski
发明人： Brent S. Baxter , Stephen S. Pawlowski
IPC分类号： G06F1318
CPC分类号： G06F13/161
摘要： Access to a memory is arbitrated by a memory arbiter. A plurality of first counters in the memory arbiter decrements service periods associated with isochronous memory requests, and a second counter decrements a service period associated with asynchronous memory requests, with the service periods for the first and second memory requests together comprising a schedule period. A scheduler logic circuit receives isochronous and asynchronous memory requests and generates a grant signal to service a received asynchronous request during the schedule period if time remains in the second counter or if there are no pending isochronous memory requests.
摘要翻译：存储器的访问由存储器仲裁器仲裁。存储器仲裁器中的多个第一计数器减少与同步存储器请求相关联的服务周期，并且第二计数器递减与异步存储器请求相关联的服务周期，第一和第二存储器请求的服务周期一起包括调度周期。调度器逻辑电路接收等时和异步存储器请求，并且如果时间保留在第二计数器中或者如果没有未决等时存储器请求，则在调度周期期间生成授权信号来服务接收到的异步请求。

8. 发明授权

US06412049B1 Method for minimizing CPU memory latency while transferring streaming data 有权
标题翻译：传输流数据时最小化CPU内存延迟的方法
公开(公告)号：US06412049B1
公开(公告)日：2002-06-25
申请号：US09465528
申请日：1999-12-16
申请人： Brent S. Baxter , John I. Garney , Stephen S. Pawlowski
发明人： Brent S. Baxter , John I. Garney , Stephen S. Pawlowski
IPC分类号： G06F1318
CPC分类号： G06F13/161
摘要： Access to a memory is arbitrated by defining a schedule period having service periods for isochronous and asynchronous memory requests. Received isochronous requests are serviced during their respective service periods, and if an asynchronous request is received during an isochronous service period , the isochronous service period is suspended and the asynchronous request is serviced, provided that time remains in the asynchronous service period or there is no isochronous request pending. Otherwise, service of the asynchronous request is delayed until the next schedule period. Service time for isochronous request are therefore guaranteed and scheduled around asynchronous memory request. If there are any maintenance events signaled, the service period for the asynchronous request may be correspondingly decreased while the maintenance event is performed.
摘要翻译：通过定义具有等时和异步存储器请求的服务周期的调度周期来仲裁对存储器的访问。接收到的同步请求在其各自的服务周期内被服务，并且如果在同步服务周期期间接收到异步请求，则等待服务周期被暂停并且异步请求被服务，只要时间保持在异步服务周期或没有等时请求待处理。否则，异步请求的服务将被延迟到下一个调度周期。因此，等时请求的服务时间将围绕异步存储器请求进行保证和调度。如果发生了任何维护事件，则可以相应地减少异步请求的服务周期，同时执行维护事件。

9. 发明授权

US06363461B1 Apparatus for memory resource arbitration based on dedicated time slot allocation 有权
标题翻译：基于专用时隙分配的存储资源仲裁装置
公开(公告)号：US06363461B1
公开(公告)日：2002-03-26
申请号：US09465537
申请日：1999-12-16
申请人： Stephen S. Pawlowski , Brent S. Baxter
发明人： Stephen S. Pawlowski , Brent S. Baxter
IPC分类号： G06F1318
CPC分类号： G06F13/1605
摘要： Access to a memory is arbitrated by a memory arbiter. A plurality of first counters in the memory arbiter decrements service periods associated with isochronous memory requests, and a second counter decrements a service period associated with asynchronous memory requests, with the service periods for the first and second memory requests together comprising a schedule period. A scheduler logic circuit receives isochronous and asynchronous memory requests and generates a grant signal to service a received asynchronous request during the schedule period if time remains in the second counter. If there are any maintenance events signaled, the memory arbiter may correspondingly decrease the service period for the asynchronous request while the maintenance event is performed.
摘要翻译：存储器的访问由存储器仲裁器仲裁。存储器仲裁器中的多个第一计数器减少与同步存储器请求相关联的服务周期，并且第二计数器递减与异步存储器请求相关联的服务周期，第一和第二存储器请求的服务周期一起包括调度周期。调度器逻辑电路接收等时和异步存储器请求，并且如果时间保留在第二计数器中，则生成授权信号以在调度周期期间服务所接收的异步请求。如果有任何维护事件发出信号，则在执行维护事件时，存储器仲裁器可以相应地减少异步请求的服务周期。

10. 发明授权

US07616220B2 Spatio-temporal generation of motion blur 失效
标题翻译：运动模糊的时空生成
公开(公告)号：US07616220B2
公开(公告)日：2009-11-10
申请号：US10747322
申请日：2003-12-23
申请人： Brent S. Baxter
发明人： Brent S. Baxter
IPC分类号： G06T15/70
CPC分类号： G06T13/80
摘要： Embodiments of the present invention blend frames over a specified spatial and temporal extent to produce a smoothly animated appearance at a reduced frame rate. As the window moves further or closer to the viewer, motion blur may be accomplished by a combination of spatial and temporal averaging. Spatial averaging is used in conjunction with temporal averaging to reduce the rate at which images, including desktop images, are composed and to reduce the amount of graphics memory bandwidth needed for the composition.
摘要翻译：本发明的实施例在特定的空间和时间范围内混合帧以在降低的帧速率下产生平滑的动画外观。当窗口进一步或更靠近观察者时，可以通过空间和时间平均的组合来实现运动模糊。空间平均与时间平均结合使用，以降低包括桌面图像在内的图像的组合速率，并减少组合所需的图形内存带宽。

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