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1. 发明授权

US06415367B1 Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration scheme 有权
标题翻译：用于在基于时隙的存储器仲裁方案中减少异步服务延迟的装置
公开(公告)号：US06415367B1
公开(公告)日：2002-07-02
申请号：US09465527
申请日：1999-12-16
申请人： Brent S. Baxter , Stephen S. Pawlowski
发明人： Brent S. Baxter , Stephen S. Pawlowski
IPC分类号： G06F1318
CPC分类号： G06F13/161
摘要： Access to a memory is arbitrated by a memory arbiter. A plurality of first counters in the memory arbiter decrements service periods associated with isochronous memory requests, and a second counter decrements a service period associated with asynchronous memory requests, with the service periods for the first and second memory requests together comprising a schedule period. A scheduler logic circuit receives isochronous and asynchronous memory requests and generates a grant signal to service a received asynchronous request during the schedule period if time remains in the second counter or if there are no pending isochronous memory requests.
摘要翻译：存储器的访问由存储器仲裁器仲裁。存储器仲裁器中的多个第一计数器减少与同步存储器请求相关联的服务周期，并且第二计数器递减与异步存储器请求相关联的服务周期，第一和第二存储器请求的服务周期一起包括调度周期。调度器逻辑电路接收等时和异步存储器请求，并且如果时间保留在第二计数器中或者如果没有未决等时存储器请求，则在调度周期期间生成授权信号来服务接收到的异步请求。

2. 发明授权

US06412049B1 Method for minimizing CPU memory latency while transferring streaming data 有权
标题翻译：传输流数据时最小化CPU内存延迟的方法
公开(公告)号：US06412049B1
公开(公告)日：2002-06-25
申请号：US09465528
申请日：1999-12-16
申请人： Brent S. Baxter , John I. Garney , Stephen S. Pawlowski
发明人： Brent S. Baxter , John I. Garney , Stephen S. Pawlowski
IPC分类号： G06F1318
CPC分类号： G06F13/161
摘要： Access to a memory is arbitrated by defining a schedule period having service periods for isochronous and asynchronous memory requests. Received isochronous requests are serviced during their respective service periods, and if an asynchronous request is received during an isochronous service period , the isochronous service period is suspended and the asynchronous request is serviced, provided that time remains in the asynchronous service period or there is no isochronous request pending. Otherwise, service of the asynchronous request is delayed until the next schedule period. Service time for isochronous request are therefore guaranteed and scheduled around asynchronous memory request. If there are any maintenance events signaled, the service period for the asynchronous request may be correspondingly decreased while the maintenance event is performed.
摘要翻译：通过定义具有等时和异步存储器请求的服务周期的调度周期来仲裁对存储器的访问。接收到的同步请求在其各自的服务周期内被服务，并且如果在同步服务周期期间接收到异步请求，则等待服务周期被暂停并且异步请求被服务，只要时间保持在异步服务周期或没有等时请求待处理。否则，异步请求的服务将被延迟到下一个调度周期。因此，等时请求的服务时间将围绕异步存储器请求进行保证和调度。如果发生了任何维护事件，则可以相应地减少异步请求的服务周期，同时执行维护事件。

3. 发明授权

US06363461B1 Apparatus for memory resource arbitration based on dedicated time slot allocation 有权
标题翻译：基于专用时隙分配的存储资源仲裁装置
公开(公告)号：US06363461B1
公开(公告)日：2002-03-26
申请号：US09465537
申请日：1999-12-16
申请人： Stephen S. Pawlowski , Brent S. Baxter
发明人： Stephen S. Pawlowski , Brent S. Baxter
IPC分类号： G06F1318
CPC分类号： G06F13/1605
摘要： Access to a memory is arbitrated by a memory arbiter. A plurality of first counters in the memory arbiter decrements service periods associated with isochronous memory requests, and a second counter decrements a service period associated with asynchronous memory requests, with the service periods for the first and second memory requests together comprising a schedule period. A scheduler logic circuit receives isochronous and asynchronous memory requests and generates a grant signal to service a received asynchronous request during the schedule period if time remains in the second counter. If there are any maintenance events signaled, the memory arbiter may correspondingly decrease the service period for the asynchronous request while the maintenance event is performed.
摘要翻译：存储器的访问由存储器仲裁器仲裁。存储器仲裁器中的多个第一计数器减少与同步存储器请求相关联的服务周期，并且第二计数器递减与异步存储器请求相关联的服务周期，第一和第二存储器请求的服务周期一起包括调度周期。调度器逻辑电路接收等时和异步存储器请求，并且如果时间保留在第二计数器中，则生成授权信号以在调度周期期间服务所接收的异步请求。如果有任何维护事件发出信号，则在执行维护事件时，存储器仲裁器可以相应地减少异步请求的服务周期。

4. 发明授权

US09547615B2 Peripheral protocol negotiation 有权
标题翻译：外设协议协商
公开(公告)号：US09547615B2
公开(公告)日：2017-01-17
申请号：US13977822
申请日：2011-10-01
申请人： Dennis M. Bell , Stephen S. Pawlowski
发明人： Dennis M. Bell , Stephen S. Pawlowski
IPC分类号： G06F13/00 , G06F13/38 , G06F13/14 , G06F9/44 , G06F13/42
CPC分类号： G06F13/387 , G06F9/4413 , G06F13/14 , G06F13/38 , G06F13/4221
摘要： Systems and methods of operating a computing system may involve utilizing at least one of a peripheral protocol negotiation and a universal connector to determine a peripheral device protocol, and reconfiguring a computer device to accommodate that peripheral device protocol. Upon such a reconfiguration, the peripheral protocol negotiation may “step aside”, and one or more subsequent communications between a host computer and the peripheral device utilizing the peripheral device protocol may start.
摘要翻译：操作计算系统的系统和方法可以包括利用外围协议协商和通用连接器中的至少一个来确定外围设备协议，以及重新配置计算机设备以适应该外围设备协议。在这样的重新配置中，外围协议协商可以“搁置”，并且可以开始使用外围设备协议的主计算机和外围设备之间的一个或多个后续通信。

5. 发明申请

US20150278068A1 INITIALIZATION TRACE OF A COMPUTING DEVICE 审中-公开
标题翻译：计算机设备的初始化跟踪
公开(公告)号：US20150278068A1
公开(公告)日：2015-10-01
申请号：US14226612
申请日：2014-03-26
申请人： Robert C. Swanson , C. Brendan Traw , Vincent J. Zimmer , Mallik Bulusu , John R. Lindsley , Mahesh S. Natu , Dimitrios Ziakas , Robert W. Cone , Madhusudhan Rangarajan , Babak Nikjou , Kirk D. Brannock , Russell J. Wunderlich , Miles F. Schwartz , Stephen S. Pawlowski
发明人： Robert C. Swanson , C. Brendan Traw , Vincent J. Zimmer , Mallik Bulusu , John R. Lindsley , Mahesh S. Natu , Dimitrios Ziakas , Robert W. Cone , Madhusudhan Rangarajan , Babak Nikjou , Kirk D. Brannock , Russell J. Wunderlich , Miles F. Schwartz , Stephen S. Pawlowski
IPC分类号： G06F11/34 , G06F9/44
CPC分类号： G06F11/3476 , G06F9/4403 , G06F9/4416 , G06F11/1417 , G06F21/575 , G06F2201/84
摘要： Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.
摘要翻译：平台控制器，计算机可读存储介质以及与计算设备的初始化相关联的方法。在实施例中，平台控制器可以包括与引导控制器耦合的引导控制器和一个或多个非易失性存储器模块。在实施例中，一个或多个非易失性存储器模块可以具有存储在其上的第一指令和第二指令。当由托管平台控制器的计算设备的处理器执行时，第一指令可以引起计算设备的初始化。第二指令在由引导控制器执行时可能导致引导控制器监视计算设备执行第一指令的至少一部分，并且可以生成第一指令的执行的监视部分的跟踪。在实施例中，迹线可以存储在一个或多个非易失性存储器模块中。可以描述和/或要求保护其他实施例。

6. 发明授权

US06807592B2 Quad pumped bus architecture and protocol 失效
标题翻译：四泵浦总线架构和协议
公开(公告)号：US06807592B2
公开(公告)日：2004-10-19
申请号：US09925691
申请日：2001-08-10
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.
摘要翻译：双向多点处理器总线连接到多个总线代理。可以通过以多抽头信令模式操作总线来增加总线吞吐量，其中多个信息元素以驱动代理以总线时钟频率的倍数的速率被驱动到总线上。驱动代理还激活选通以识别信息元素的采样点。可以例如使用双泵浦信号模式来驱动请求的信息元素，其中在一个总线时钟周期期间驱动两个信息元素。数据线传输的数据元素例如可以使用四泵浦信号模式来驱动，其中四个数据元件在一个总线时钟周期内被驱动。可以以偏移或交错布置临时地激活多个选通信号，以减少选通信号的频率。可以通过仅使用选通信号的一种类型的边缘（例如，上升沿或下降沿）来提高采样对称性，以识别采样点。

7. 发明授权

US06804735B2 Response and data phases in a highly pipelined bus architecture 失效
标题翻译：高度流水线总线架构中的响应和数据阶段
公开(公告)号：US06804735B2
公开(公告)日：2004-10-12
申请号：US09784244
申请日：2001-02-14
申请人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
发明人： Gurbir Singh , Robert J. Greiner , Stephen S. Pawlowski , David L. Hill , Donald D. Parker
IPC分类号： G06F1300
CPC分类号： G06F13/4217
摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic to track a plurality of transactions comprising a transaction N-1 and a transaction N, the bus controller being capable of asserting the target ready signal for transaction N if the bus agent is asserting the data busy signal for the transaction N-1 and deasserts the data busy signal.
摘要翻译：可用于增强的高流水线总线架构中的总线代理。在一个实施例中，总线代理包括目标就绪接口，用于一组响应信号的一组响应接口和数据总线忙接口以及用于总线时钟信号的总线时钟接口。该实施例的总线代理还包括总线控制器逻辑以跟踪包括事务N-1和事务N的多个事务，总线控制器能够为事务N断言目标就绪信号，如果总线代理正在断言数据忙信号用于事务N-1，并取消对数据忙信号的否定。

8. 发明授权

US06401153B2 Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals 有权
标题翻译：将地址和数据线上的中断请求信号转换为中断消息信号的机制
公开(公告)号：US06401153B2
公开(公告)日：2002-06-04
申请号：US09329001
申请日：1999-06-08
申请人： Stephen S. Pawlowski
发明人： Stephen S. Pawlowski
IPC分类号： G06F946
CPC分类号： G06F13/24
摘要： In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals. A redirection table includes a send pending bit to be set in response to either the interrupt request signal at the dedicated interrupt ports or in response to the decode signal.
摘要翻译：在本发明的一个实施例中，一种装置包括用于接收地址信号和数据信号形式的中断请求信号的地址和数据端口。该装置还包括用于接收地址信号和数据信号中的至少一些的解码逻辑，并且在解码逻辑的多个解码输出行之一提供解码信号。重定向表包括响应于解码信号设置的发送挂起位。在另一个实施例中，装置包括用于接收中断请求信号的专用中断端口。该装置还包括能够以地址信号和数据信号的形式接收中断请求信号的地址和数据端口，以及解码逻辑，以便响应于接收到中断请求信号的接收而在多条解码输出线之一提供解码信号地址信号和数据信号的形式。重定向表包括响应于专用中断端口处的中断请求信号或响应于解码信号而被设置的发送挂起位。

9. 发明授权

US5696910A Method and apparatus for tracking transactions in a pipelined bus 失效
标题翻译：用于跟踪流水线总线中的交易的方法和装置
公开(公告)号：US5696910A
公开(公告)日：1997-12-09
申请号：US533919
申请日：1995-09-26
申请人： Stephen S. Pawlowski
发明人： Stephen S. Pawlowski
IPC分类号： G06F13/42 , H01J13/00 , G06F13/38
CPC分类号： G06F13/4217
摘要： A method and apparatus for tracking transactions in a pipelined bus includes a bus state tracking queue and control logic. The bus state tracking queue maintains a record of bus transaction information for each of a plurality of transactions pending on the bus. The control logic, coupled to the bus state tracking queue, updates the status of the plurality of transactions in the bus state tracking queue as the transactions progress through the pipeline.
摘要翻译：用于跟踪流水线总线中的事务的方法和装置包括总线状态跟踪队列和控制逻辑。总线状态跟踪队列为总线上待处理的多个事务中的每一个维护总线事务信息的记录。当事务通过流水线进行时，耦合到总线状态跟踪队列的控制逻辑更新总线状态跟踪队列中的多个事务的状态。

10. 发明授权

US5550533A High bandwidth self-timed data clocking scheme for memory bus implementation 失效
标题翻译：用于存储器总线实现的高带宽自定时数据时钟方案
公开(公告)号：US5550533A
公开(公告)日：1996-08-27
申请号：US339635
申请日：1994-11-14
申请人： Stephen S. Pawlowski
发明人： Stephen S. Pawlowski
IPC分类号： G06F13/42 , H04L1/16 , G06F1/12 , H04Q1/30
CPC分类号： G06F13/4239
摘要： A clocking scheme for transferring data between electronic devices. The clocking scheme includes sending a data request signal from a first device to a second device during a first system clocking period. The second device then sends the requested data and a corresponding data validation signal to the first device. The data validation signal latches the data into the second device. The data is latched by the validation signal in a time period that is typically shorter than the clocking period of the system clock.
摘要翻译：用于在电子设备之间传输数据的时钟方案。时钟方案包括在第一系统时钟周期期间将数据请求信号从第一设备发送到第二设备。然后，第二设备将所请求的数据和相应的数据验证信号发送到第一设备。数据验证信号将数据锁存到第二个设备中。在通常比系统时钟的时钟周期更短的时间段内，该数据被验证信号锁存。

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