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    • 3. 发明申请
    • SEMICONDUCTOR DEVICE, WIRELESS COMMUNICATION DEVICE AND METHOD FOR GENERATING A SYNTHESIZED FREQUENCY SIGNAL
    • 半导体器件,无线通信设备和用于产生合成频率信号的方法
    • US20110151804A1
    • 2011-06-23
    • US13059085
    • 2008-08-26
    • Norman BeamishNiall KearneyAidan Murphy
    • Norman BeamishNiall KearneyAidan Murphy
    • H04B1/40H03B21/00
    • H03L7/23H03L7/0814H03L7/197
    • A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto.
    • 半导体器件包括被配置为接收参考信号并且提供输出频率信号的合成频率产生逻辑。 合成频率产生逻辑包括分配器逻辑,其被布置为接收参考信号并产生包括具有等于参考信号的N倍的周期的频率的分频信号。 合成频率产生逻辑还被布置为产生合成频率信号,该合成频率信号包括具有等于分频信号的周期等于1 / M的周期的频率。 合成频率产生逻辑包括或可操作地耦合到决策逻辑模块,并且包括或可操作地耦合到开关逻辑模块,使得决策逻辑模块被布置为确定在使用合成频率信号时是否产生近似整数杂散,以及 配置切换逻辑模块以响应于此选择合成频率信号。
    • 4. 发明授权
    • Semiconductor device, wireless communication device and method for generating a synthesized frequency signal
    • 半导体装置,无线通信装置以及用于产生合成频率信号的方法
    • US08630593B2
    • 2014-01-14
    • US13059085
    • 2008-08-26
    • Norman BeamishNiall KearneyAidan Murphy
    • Norman BeamishNiall KearneyAidan Murphy
    • H04B1/40
    • H03L7/23H03L7/0814H03L7/197
    • A semiconductor device comprises synthesized frequency generation logic arranged to receive a reference signal, and to provide an output frequency signal. The synthesized frequency generation logic comprises divider logic arranged to receive the reference signal and to generate a divided signal comprising a frequency with a period equal to N times that of the reference signal. The synthesized frequency generation logic is further arranged to generate the synthesized frequency signal comprising a frequency with a period equal to 1/M that of the divided signal. The synthesized frequency generation logic comprises or is operably coupled to decision logic module and comprises or is operably coupled to a switching logic module such that the decision logic module is arranged to determine whether a near-integer spur arises in using the synthesized frequency signal, and configures the switching logic module to select the synthesized frequency signal in response thereto.
    • 半导体器件包括被配置为接收参考信号并且提供输出频率信号的合成频率产生逻辑。 合成频率产生逻辑包括分配器逻辑,其被布置为接收参考信号并产生包括具有等于参考信号的N倍的周期的频率的分频信号。 合成频率产生逻辑还被布置为产生合成频率信号,该合成频率信号包括具有等于分频信号的周期等于1 / M的周期的频率。 合成频率产生逻辑包括或可操作地耦合到决策逻辑模块,并且包括或可操作地耦合到开关逻辑模块,使得决策逻辑模块被布置为确定在使用合成频率信号时是否产生近似整数杂散,以及 配置切换逻辑模块以响应于此选择合成频率信号。
    • 5. 发明授权
    • Card holder
    • 持卡人
    • US09437121B2
    • 2016-09-06
    • US13984379
    • 2012-02-08
    • Aidan Murphy
    • Aidan Murphy
    • G09F1/10G09F23/06G09F13/18
    • G09F1/10G09F13/18G09F23/06
    • A holder (100) for a folded card (102), the folded card (102) being of the type having a spine (108) and at least two sheets (110). The holder (100) having a holder support (104) for engagement with a surface for preventing the holder (100) being disturbed in an outdoor environment and a card supporting arrangement (106) mounted on the holder support (104). The card supporting arrangement (104) having an assembly for supporting the spine (108) of the folded card (102) and for engaging at least a portion of the sheets (110) of the folded card (102) on opposing sides of the spine (108) holding the folded card (102) open at a pre-determined angle.
    • 用于折叠卡(102)的保持器(100),所述折叠卡(102)是具有脊(108)和至少两个片(110)的类型。 所述保持器(100)具有用于与用于防止所述保持器(100)在室外环境中被干扰的表面接合的保持器支撑件(104)和安装在所述保持器支撑件(104)上的卡片支撑装置(106)。 卡支撑装置(104)具有用于支撑折叠卡(102)的脊(108)的组件,并用于与折叠卡(102)的脊柱(102)的相对侧上的至少一部分片(110)接合 (108)保持折叠卡(102)以预定角度打开。
    • 6. 发明申请
    • CARD HOLDER
    • 卡片夹
    • US20130313397A1
    • 2013-11-28
    • US13984379
    • 2012-02-08
    • Aidan Murphy
    • Aidan Murphy
    • G09F1/10
    • G09F1/10G09F13/18G09F23/06
    • A holder (100) for a folded card (102), the folded card (102) being of the type having a spine (108) and at least two sheets (110). The holder (100) having a holder support (104) for engagement with a surface for preventing the holder (100) being disturbed in an outdoor environment and a card supporting arrangement (106) mounted on the holder support (104). The card supporting arrangement (104) having an assembly for supporting the spine (108) of the folded card (102) and for engaging at least a portion of the sheets (110) of the folded card (102) on opposing sides of the spine (108) holding the folded card (102) open at a pre-determined angle.
    • 用于折叠卡(102)的保持器(100),所述折叠卡(102)是具有脊(108)和至少两个片(110)的类型。 所述保持器(100)具有用于与用于防止所述保持器(100)在室外环境中被干扰的表面接合的保持器支撑件(104)和安装在所述保持器支撑件(104)上的卡片支撑装置(106)。 卡支撑装置(104)具有用于支撑折叠卡(102)的脊(108)的组件,并且用于将折叠卡(102)的片(110)的至少一部分接合在脊柱的相对侧上 (108)保持折叠卡(102)以预定角度打开。
    • 7. 发明申请
    • TEMPERATURE COMPENSATION IN A PHASE-LOCKED LOOP
    • 相位锁定环路温度补偿
    • US20110260761A1
    • 2011-10-27
    • US13121693
    • 2008-10-17
    • Niall KearneyAidan Murphy
    • Niall KearneyAidan Murphy
    • H03L7/08
    • H03L7/099H03L1/02H03L7/10
    • An integrated circuit comprises a digital phase-locked loop for a wireless communications unit. The digital phase-locked loop comprises a voltage controlled oscillator and a digital tuning subsystem. An input of the digital tuning subsystem receives the output signal from the voltage controlled oscillator, and an output of the digital tuning subsystem is supplied to the voltage controlled oscillator. A digital voltage generator is adapted to store at least two predetermined forcing voltages. The digital voltage generator is adapted to select one of the at least two predetermined forcing voltages, in dependence on a current temperature value, and to supply it as a forcing voltage to an input of the voltage controlled oscillator, prior to the phase locked loop achieving lock. A wireless communication unit and a method of tuning a phase-locked loop are also provided.
    • 集成电路包括用于无线通信单元的数字锁相环。 数字锁相环包括压控振荡器和数字调谐子系统。 数字调谐子系统的输入接收来自压控振荡器的输出信号,数字调谐子系统的输出端被提供给压控振荡器。 数字电压发生器适于存储至少两个预定的强制电压。 数字电压发生器适于根据当前温度值选择至少两个预定的强制电压中的一个,并且在锁相环实现之前将其作为强制电压提供给压控振荡器的输入 锁。 还提供了无线通信单元和调谐锁相环的方法。