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1. 发明授权

US08294236B2 Semiconductor device having dual-STI and manufacturing method thereof 有权
标题翻译：具有双STI的半导体器件及其制造方法
公开(公告)号：US08294236B2
公开(公告)日：2012-10-23
申请号：US12946311
申请日：2010-11-15
申请人： Noriyuki Mitsuhira , Takehiko Nakahara , Yasusuke Suzuki , Jun Sumino
发明人： Noriyuki Mitsuhira , Takehiko Nakahara , Yasusuke Suzuki , Jun Sumino
IPC分类号： H01L21/70
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/11536
摘要： A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
摘要翻译：具有存储单元区域和外围电路区域的半导体器件包括硅衬底和由在硅衬底的表面上形成的氧化硅膜实现的隔离结构。存储器单元区域中的隔离结构的深度小于外围电路区域中的隔离结构的深度，并且隔离结构在存储单元区域中的隔离高度与隔离的隔离高度基本相同外围电路区域的结构。因此可以提高半导体器件的可靠性。

2. 发明授权

US07858490B2 Semiconductor device having dual-STI and manufacturing method thereof 有权
标题翻译：具有双STI的半导体器件及其制造方法
公开(公告)号：US07858490B2
公开(公告)日：2010-12-28
申请号：US12076038
申请日：2008-03-13
申请人： Noriyuki Mitsuhira , Takehiko Nakahara , Yasusuke Suzuki , Jun Sumino
发明人： Noriyuki Mitsuhira , Takehiko Nakahara , Yasusuke Suzuki , Jun Sumino
IPC分类号： H01L21/76
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/11536
摘要： A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
摘要翻译：具有存储单元区域和外围电路区域的半导体器件包括硅衬底和由在硅衬底的表面上形成的氧化硅膜实现的隔离结构。存储器单元区域中的隔离结构的深度小于外围电路区域中的隔离结构的深度，并且隔离结构在存储单元区域中的隔离高度与隔离的隔离高度基本相同外围电路区域的结构。因此可以提高半导体器件的可靠性。

3. 发明申请

US20080213971A1 Semiconductor device having dual-STI and manufacturing method thereof 有权
标题翻译：具有双STI的半导体器件及其制造方法
公开(公告)号：US20080213971A1
公开(公告)日：2008-09-04
申请号：US12076038
申请日：2008-03-13
申请人： Noriyuki Mitsuhira , Takehiko Nakahara , Yasusuke Suzuki , Jun Sumino
发明人： Noriyuki Mitsuhira , Takehiko Nakahara , Yasusuke Suzuki , Jun Sumino
IPC分类号： H01L21/762
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/11536
摘要： A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
摘要翻译：具有存储单元区域和外围电路区域的半导体器件包括硅衬底和由在硅衬底的表面上形成的氧化硅膜实现的隔离结构。存储器单元区域中的隔离结构的深度小于外围电路区域中的隔离结构的深度，并且隔离结构在存储单元区域中的隔离高度与隔离的隔离高度基本相同外围电路区域的结构。因此可以提高半导体器件的可靠性。

4. 发明申请

US20060035437A1 Semiconductor device having dual-STI and manufacturing method thereof 审中-公开
标题翻译：具有双STI的半导体器件及其制造方法
公开(公告)号：US20060035437A1
公开(公告)日：2006-02-16
申请号：US11200262
申请日：2005-08-10
申请人： Noriyuki Mitsuhira , Takehiko Nakahara , Yasusuke Suzuki , Jun Sumino
发明人： Noriyuki Mitsuhira , Takehiko Nakahara , Yasusuke Suzuki , Jun Sumino
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/1052 , H01L27/11536
摘要： A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
摘要翻译：具有存储单元区域和外围电路区域的半导体器件包括硅衬底和由在硅衬底的表面上形成的氧化硅膜实现的隔离结构。存储器单元区域中的隔离结构的深度小于外围电路区域中的隔离结构的深度，并且隔离结构在存储单元区域中的隔离高度与隔离的隔离高度基本相同外围电路区域的结构。因此可以提高半导体器件的可靠性。

5. 发明授权

US08519377B2 Nonvolatile memory device, nonvolatile memory device group, and manufacturing method thereof 有权
公开(公告)号：US08519377B2
公开(公告)日：2013-08-27
申请号：US13252643
申请日：2011-10-04
申请人： Jun Sumino , Motonari Honda
发明人： Jun Sumino , Motonari Honda
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L45/1246 , H01L27/228 , H01L27/2436 , H01L27/2472 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/085 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
摘要： A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.

6. 发明授权

US08476614B2 Memory device and fabrication process thereof 有权
标题翻译：存储器件及其制造工艺
公开(公告)号：US08476614B2
公开(公告)日：2013-07-02
申请号：US12906214
申请日：2010-10-18
申请人： Jun Sumino , Shuichiro Yasuda
发明人： Jun Sumino , Shuichiro Yasuda
IPC分类号： H01L47/00
CPC分类号： H01L45/141 , G11C13/0002 , H01L27/2472 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/165 , H01L45/1666
摘要： A memory device that includes a resistive-change memory element, the memory device includes: a first memory element that includes a first resistive-change layer and a first electrode connected to the first resistive-change layer; and a second memory element that includes a second resistive-change layer and a second electrode connected to the second resistive-change layer, wherein at least one of the thickness and the material of the second resistive-change layer and the area of the second electrode in contact with the second resistive-change layer is different from the corresponding one of the thickness and the material of the first resistive-change layer and the area of the first electrode in contact with the first resistive-change layer.
摘要翻译：一种包括电阻变化存储元件的存储器件，所述存储器件包括：第一存储器元件，其包括第一电阻变化层和连接到所述第一电阻变化层的第一电极; 以及第二存储元件，其包括连接到第二电阻变化层的第二电阻变化层和第二电极，其中第二电阻变化层的厚度和材料中的至少一个以及第二电极的面积与第二电阻变化层接触的不同于第一电阻变化层的厚度和材料中的相应一个以及与第一电阻变化层接触的第一电极的面积。

7. 发明授权

US08242552B2 Storage element, method of manufacturing same, and semiconductor storage device 有权
标题翻译：存储元件及其制造方法以及半导体存储装置
公开(公告)号：US08242552B2
公开(公告)日：2012-08-14
申请号：US12729664
申请日：2010-03-23
申请人： Jun Sumino
发明人： Jun Sumino
IPC分类号： H01L47/00 , H01L29/79 , H01L21/20
CPC分类号： H01L45/085 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/16
摘要： Disclosed herein is a storage element including: a first electrode; a second electrode formed in a position opposed to the first electrode; and a variable-resistance layer formed so as to be interposed between the first electrode and the second electrode. The first electrode is a tubular object, and is formed so as to be thicker on an opposite side from the variable-resistance layer than on a side of the variable-resistance layer.
摘要翻译：本文公开了一种存储元件，包括：第一电极; 形成在与所述第一电极相对的位置的第二电极; 以及可变电阻层，形成为插入在第一电极和第二电极之间。第一电极是管状物体，并且形成为在可变电阻层的相对侧比在可变电阻层的侧面更厚。

8. 发明申请

US20120091415A1 NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE GROUP, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器件，非易失性存储器件组及其制造方法
公开(公告)号：US20120091415A1
公开(公告)日：2012-04-19
申请号：US13252643
申请日：2011-10-04
申请人： Jun Sumino , Motonari Honda
发明人： Jun Sumino , Motonari Honda
IPC分类号： H01L45/00 , H01L21/62
CPC分类号： H01L45/1246 , H01L27/228 , H01L27/2436 , H01L27/2472 , H01L43/08 , H01L43/10 , H01L45/06 , H01L45/085 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
摘要： A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.
摘要翻译：非易失性存储器件组包括：（A）第一绝缘层; （B）第二绝缘层，其具有与所述第一凹部连通的第一凹部和第二凹部，其宽度大于所述第一凹部的宽度，并且设置在所述第一绝缘层上; （C）多个电极，其设置在第一绝缘层中，其顶表面从第一凹部的底表面露出; （D）形成在第一凹部和第二凹部的侧壁和底表面上的信息存储层; 和（E）填充在由第二凹部中的信息存储层包围的空间中的导电材料层。

9. 发明授权

US07326627B2 Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device 有权
标题翻译：制造具有沟槽隔离结构和所得半导体器件的半导体器件的方法
公开(公告)号：US07326627B2
公开(公告)日：2008-02-05
申请号：US11822467
申请日：2007-07-06
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L21/76
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译：本发明的制造方法包括以下步骤：在半导体衬底的主表面上提供氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除氧化膜以暴露上沟槽的底部的至少一部分，并允许氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

10. 发明申请

US20050139908A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050139908A1
公开(公告)日：2005-06-30
申请号：US11045101
申请日：2005-01-31
申请人： Jun Sumino , Satoshi Shimizu
发明人： Jun Sumino , Satoshi Shimizu
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11521 , H01L21/76232 , H01L21/76235 , H01L27/115
摘要： A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms that bring into contact with element isolation oxide film and element isolation oxide film, respectively; and a polysilicon film, formed on tunnel oxide film, having a thickness exceeding 0 and being less than 50 nm in an intermediate portion between element isolation oxide film and element isolation oxide film, and being thinner than the above thickness on birds beak portions. Thereby, it is possible to provide a semiconductor device wherein birds beaks are formed in the gate insulating film so as to have the desired dimensions and wherein the gate insulating film has excellent electrical characteristics.
摘要翻译：半导体器件包括：具有主表面的硅衬底，其中形成沟槽; 填充在沟槽中的元件隔离氧化膜; 形成在元件隔离氧化膜和元件隔离氧化膜之间的主表面上的隧道氧化膜，分别具有与元件隔离氧化膜和元件隔离氧化膜接触的鸟喙部分的鸟嘴部分; 以及在元件隔离氧化膜和元件隔离氧化膜之间的中间部分中，在隧道氧化膜上形成的厚度超过0且小于50nm的多晶硅膜，并且在鸟嘴部分上比上述厚度薄。由此，可以提供一种半导体器件，其中在栅极绝缘膜中形成鸟喙以具有期望的尺寸，并且其中栅极绝缘膜具有优异的电气特性。

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