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1. 发明申请

US20060110592A1 Acrylic film and laminates comprising the same 有权
标题翻译：丙烯酸膜和包含其的层压制品
公开(公告)号：US20060110592A1
公开(公告)日：2006-05-25
申请号：US10531282
申请日：2002-12-19
申请人： Norito Doi , Takao Shibata , Yoichi Matsumura , Shigemi Matsumoto
发明人： Norito Doi , Takao Shibata , Yoichi Matsumura , Shigemi Matsumoto
IPC分类号： B32B27/30 , C08L51/00
CPC分类号： C08L33/10 , C08J5/18 , C08J2333/10 , C08J2351/04 , C08L33/12 , C08L51/04 , Y10T428/254 , Y10T428/31935 , C08L2666/24
摘要： To provide an acrylic film, composed of a resin composition (C) that includes an acrylic graft copolymer (A) containing an acrylic ester rubber-like polymer and a methacrylic polymer (B) containing 80% by weight or more of methyl methacrylate, wherein (1) the content of the acrylic ester rubber-like polymer in the resin composition (C) is 5% by weight or more and 30% by weight or less, (2) the average particle size of the acrylic ester rubber-like polymer is 500 to 2000 Å, (3) the relationship between the average particle size d (Å) of the acrylic ester rubber-like polymer and the amount w (% by weight) of crosslinking agent used in the acrylic ester rubber-like polymer satisfies the following equation: 0.002d≦w≦0.005d, (4) the graft ratio of the acrylic graft copolymer (A) is 30% or more and 200% or less, and (5) the reduced viscosity of methyl ethyl ketone soluble matter in the resin composition (C) is 0.2 to 0.8 dl/g.
摘要翻译：为了提供一种由含有丙烯酸酯类橡胶状聚合物的丙烯酸接枝共聚物（A）和含有80重量％以上的甲基丙烯酸甲酯的甲基丙烯酸系聚合物（B）的树脂组合物（C）构成的丙烯酸系膜，其中，（1）树脂组合物（C）中丙烯酸酯类橡胶状聚合物的含量为5重量％以上且30重量％以下，（2）丙烯酸酯类橡胶状聚合物的平均粒径为500〜2000埃，（3）丙烯酸酯类橡胶状聚合物的平均粒径d（）与丙烯酸酯类橡胶状聚合物中使用的交联剂的w（重量％）的量之间的关系满足以下等式：0.002d <= w <= 0.005d，（4）丙烯酸接枝共聚物（A）的接枝率为30％以上且200％以下，（5）甲基乙基酮的比浓粘度树脂组合物（C）中的可溶物质为0.2〜0.8dl / g。

2. 发明授权

US07195816B2 Acrylic film and laminates comprising the same 有权
标题翻译：丙烯酸膜和包含其的层压制品
公开(公告)号：US07195816B2
公开(公告)日：2007-03-27
申请号：US10531282
申请日：2002-12-19
申请人： Norito Doi , Takao Shibata , Yoichi Matsumura , Shigemi Matsumoto
发明人： Norito Doi , Takao Shibata , Yoichi Matsumura , Shigemi Matsumoto
IPC分类号： B32B5/16 , B32B27/30 , C08G63/48 , C08L31/02 , C08L33/06
CPC分类号： C08L33/10 , C08J5/18 , C08J2333/10 , C08J2351/04 , C08L33/12 , C08L51/04 , Y10T428/254 , Y10T428/31935 , C08L2666/24
摘要： To provide an acrylic film, composed of a resin composition (C) that includes an acrylic graft copolymer (A) containing an acrylic ester rubber-like polymer and a methacrylic polymer (B) containing 80% by weight or more of methyl methacrylate, wherein (1) the content of the acrylic ester rubber-like polymer in the resin composition (C) is 5% by weight or more and 30% by weight or less, (2) the average particle size of the acrylic ester rubber-like polymer is 500 to 2000 Å, (3) the relationship between the average particle size d (Å) of the acrylic ester rubber-like polymer and the amount w (% by weight) of crosslinking agent used in the acrylic ester rubber-like polymer satisfies the following equation: 0.002d≦w≦0.005d, (4) the graft ratio of the acrylic graft copolymer (A) is 30% or more and 200% or less, and (5) the reduced viscosity of methyl ethyl ketone soluble matter in the resin composition (C) is 0.2 to 0.8 dl/g.
摘要翻译：为了提供一种由含有丙烯酸酯类橡胶状聚合物的丙烯酸接枝共聚物（A）和含有80重量％以上的甲基丙烯酸甲酯的甲基丙烯酸系聚合物（B）的树脂组合物（C）构成的丙烯酸系膜，其中，（1）树脂组合物（C）中丙烯酸酯类橡胶状聚合物的含量为5重量％以上且30重量％以下，（2）丙烯酸酯类橡胶状聚合物的平均粒径为500〜2000埃，（3）丙烯酸酯类橡胶状聚合物的平均粒径d（）与丙烯酸酯类橡胶状聚合物中使用的交联剂的w（重量％）的量之间的关系满足以下等式：0.002d <= w <= 0.005d，（4）丙烯酸接枝共聚物（A）的接枝率为30％以上且200％以下，（5）甲基乙基酮的比浓粘度树脂组合物（C）中的可溶物质为0.2〜0.8dl / g。

3. 发明申请

US20100041783A1 Foam and Process for Producing the Same 审中-公开
标题翻译：泡沫及其生产工艺
公开(公告)号：US20100041783A1
公开(公告)日：2010-02-18
申请号：US12440712
申请日：2007-09-11
申请人： Masaoki Goto , Yoichi Matsumura , Shuhei Taniguchi , Miaki Shibaya , Kohei Fukaya , Takaoki Saneyasu , Masaki Ichimura
发明人： Masaoki Goto , Yoichi Matsumura , Shuhei Taniguchi , Miaki Shibaya , Kohei Fukaya , Takaoki Saneyasu , Masaki Ichimura
IPC分类号： C08J9/00
CPC分类号： A61L15/425 , C08J9/141 , C08J2207/10 , C08J2383/12 , C08J2387/00
摘要： It is intended to provide a resin foam which can be preferably used for medical use, and a flexible silicone type resin foam having a water-absorbing property. The resin foam which has a low toxicity and excellent physical properties for medical use such as moisture permeability, skin compatibility and low irritation can be obtained by using a resin which has a siloxane unit and an oxyalkylene unit in its molecular structure and does not contain a unit derived from an isocyanate group. Further, the flexible silicone type resin foam having a water-absorbing property can be obtained by allowing it to have a specific resin composition and a foam structure.
摘要翻译：旨在提供一种可优选用于医疗用途的树脂泡沫，以及具有吸水性的柔性硅树脂泡沫。通过使用在分子结构中具有硅氧烷单元和氧化烯单元的树脂，并且不含有氧化烯的树脂，可以获得具有低毒性和优异物理性能的树脂发泡体，例如透湿性，皮肤相容性和低刺激性衍生自异氰酸酯基团的单元。此外，通过使其具有特定的树脂组合物和泡沫结构，可以获得具有吸水性的柔性硅氧烷型树脂发泡体。

4. 发明申请

US20050086621A1 Method for processing design data of semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路设计数据处理方法
公开(公告)号：US20050086621A1
公开(公告)日：2005-04-21
申请号：US10895821
申请日：2004-07-22
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455 , H01L21/82
CPC分类号： G06F17/5045
摘要： A circuit from which a buffer and an inverter are removed without changing logic is displayed. Such a circuit is obtained by a first or a second method. With the first method, all buffers which do not change logic and, when a clock path is divided at a branch point of wiring, all pairs of inverters located on each divided clock path are removed from the clock circuit. With the second method, a logic element located on a plurality of clock paths is copied and added to the clock circuit, all buffers which do not change logic and all pairs of inverters located between logic elements other than the above buffers are removed, and redundant partial circuits, if any, realizing the same logic and being located on a plurality of clock paths are removed. Thus, the clock circuit can be displayed so as to facilitate a designer's understanding of logic.
摘要翻译：显示缓冲器和逆变器在不改变逻辑的情况下被去除的电路。这种电路是通过第一种或第二种方法获得的。利用第一种方法，不改变逻辑的所有缓冲器，并且当在布线的分支点处划分时钟路径时，位于每个划分时钟路径上的所有反相器对都从时钟电路中去除。利用第二种方法，将位于多个时钟路径上的逻辑元件复制并添加到时钟电路中，除去不改变逻辑的所有缓冲器和位于除了上述缓冲器之外的逻辑元件之间的所有反相器对，并且冗余去除实现相同逻辑并位于多个时钟路径上的部分电路（如果有的话）。因此，可以显示时钟电路，以便于设计者对逻辑的理解。

5. 发明申请

US20050060676A1 Semiconductor integrated circuit and method for designing same 审中-公开
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US20050060676A1
公开(公告)日：2005-03-17
申请号：US10817959
申请日：2004-04-06
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F1/10 , G06F9/45 , G06F17/50 , H01L21/82 , H03L7/06
CPC分类号： G06F17/5031 , G06F1/10 , G06F17/5045 , G06F17/5059 , G06F2217/12 , Y02P90/265
摘要： The present invention provides a semiconductor integrated circuit in which timing error is not likely to occur even if there is manufacturing variability. Logic cells 16 and 17, which are included in first and second clock circuits 11 and 12, respectively, are formed by transistors of a unified size. Even if there is manufacturing variability, delay time t1 of the first clock circuit 11 and delay time t2 of the second clock circuit 12 are increased or decreased by the same amount of time. Because of this, timing error is not likely to occur in a second flip-flop 15. A logic cell included in each clock cell may be formed by a transistor having a uniform rectangular-shaped diffusion region.
摘要翻译：本发明提供一种半导体集成电路，其中即使存在制造变异性，也不可能发生定时误差。分别包括在第一和第二时钟电路11和12中的逻辑单元16和17由均匀尺寸的晶体管形成。即使存在制造变化，第一时钟电路11的延迟时间t1和第二时钟电路12的延迟时间t2增加或减少相同的时间量。因此，在第二触发器15中不可能发生定时误差。每个时钟单元中包括的逻辑单元可以由具有均匀矩形扩散区域的晶体管形成。

6. 发明授权

US08487423B2 Interconnect structure of semiconductor integrated circuit and semiconductor device including the same 有权
标题翻译：半导体集成电路的互连结构和包括其的半导体器件
公开(公告)号：US08487423B2
公开(公告)日：2013-07-16
申请号：US13169398
申请日：2011-06-27
申请人： Yoichi Matsumura , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
发明人： Yoichi Matsumura , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
摘要翻译：在具有互连层的互连层的互连层的半导体集成电路芯片中，互连的占用面积的区域有限制，具有与优先级互连方向平行的相同电位的电源互连区段之间的空位被移位在电源互连的长度和面积的限度内相对于彼此。结果，电阻的局部增加被分散，从而降低对电压降的影响。

7. 发明申请

US20080097641A1 Interconnect structure of semiconductor integrated circuit, and design method and device therefor 有权
标题翻译：半导体集成电路的互连结构及其设计方法及装置
公开(公告)号：US20080097641A1
公开(公告)日：2008-04-24
申请号：US11907999
申请日：2007-10-19
申请人： Hirofumi Miyashita , Chie Kabuo , Nobuyuki Iwauchi , Yoichi Matsumura , Fumihiro Kimura , Tatsuo Gou , Yukiji Hashimoto
发明人： Hirofumi Miyashita , Chie Kabuo , Nobuyuki Iwauchi , Yoichi Matsumura , Fumihiro Kimura , Tatsuo Gou , Yukiji Hashimoto
IPC分类号： H01L21/00 , G06F19/00
CPC分类号： G06F17/5031 , G06F17/5077 , H01L21/7682
摘要： A method for designing an interconnect structure of an interconnect layer in a semiconductor integrated circuit device includes the steps of: (a) inputting layout data of the semiconductor integrated circuit device; (b) controlling an air gap exclusion area based interconnects in the layout data; and (c) outputting layout data including the air gap exclusion area determined in the step (b).
摘要翻译：一种在半导体集成电路器件中设计互连层的互连结构的方法，包括以下步骤：（a）输入半导体集成电路器件的布局数据; （b）控制布局数据中的基于气隙排除区域的互连; 和（c）输出包括在步骤（b）中确定的气隙排除区的布局数据。

8. 发明授权

US07334210B2 Semiconductor integrated circuit and method of designing the same 有权
公开(公告)号：US07334210B2
公开(公告)日：2008-02-19
申请号：US10980269
申请日：2004-11-04
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L27/11807
摘要： In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.

9. 发明申请

US20070252258A1 Semiconductor device and semiconductor device layout designing method 有权
标题翻译：半导体器件和半导体器件布局设计方法
公开(公告)号：US20070252258A1
公开(公告)日：2007-11-01
申请号：US11790736
申请日：2007-04-27
申请人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
发明人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
IPC分类号： H01L23/02 , G08B13/14 , H01Q9/04
CPC分类号： H01L27/0203 , H01L27/118
摘要： In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.
摘要翻译：在形成连接到栅极的布线的每个布线层中，布线被布线成不覆盖天线保护元件的有源区。形成在上布线层中的布线被布线以覆盖天线保护元件的有源区域的至少一部分。

10. 发明申请

US20050097492A1 Semiconductor integrated circuit and method of designing the same 有权
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US20050097492A1
公开(公告)日：2005-05-05
申请号：US10980269
申请日：2004-11-04
申请人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
发明人： Yoichi Matsumura , Takako Ohashi , Katsuya Fujimura , Chihiro Itoh , Hiroki Taniguchi
IPC分类号： G06F17/50 , G06F9/45 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118
CPC分类号： G06F17/5068 , H01L27/11807
摘要： In a semiconductor integrated circuit, since resistance component is included in a power-supply wiring, a power-supply voltage supplied to a cell on a clock path is dropped to cause a clock skew. To avoid this problem, a cell-placement prohibiting area is set centering on a cell 10 on the clock path, and no cell for performing a logical operation is placed in this cell-placement prohibiting area. Also, a cell-placement prohibiting area may be set for each of cell groups formed of a plurality of cells closely placed together. Furthermore, a capacitive cell may be placed in the cell-placement prohibiting area.
摘要翻译：在半导体集成电路中，由于电源线中包含电阻成分，所以提供给时钟路径上的单元的电源电压下降，造成时钟偏移。为了避免这个问题，以时钟路径上的单元10为中心设置单元放置禁止区域，在该单元放置禁止区域中不设置用于执行逻辑运算的单元。此外，可以为由紧密放置在一起的多个单元形成的每个单元组设置单元布置禁止区域。此外，可以将电容单元放置在电池放置禁止区域中。

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