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1. 发明授权

US08487423B2 Interconnect structure of semiconductor integrated circuit and semiconductor device including the same 有权
标题翻译：半导体集成电路的互连结构和包括其的半导体器件
公开(公告)号：US08487423B2
公开(公告)日：2013-07-16
申请号：US13169398
申请日：2011-06-27
申请人： Yoichi Matsumura , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
发明人： Yoichi Matsumura , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
IPC分类号： H01L23/52
CPC分类号： H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
摘要翻译：在具有互连层的互连层的互连层的半导体集成电路芯片中，互连的占用面积的区域有限制，具有与优先级互连方向平行的相同电位的电源互连区段之间的空位被移位在电源互连的长度和面积的限度内相对于彼此。结果，电阻的局部增加被分散，从而降低对电压降的影响。

2. 发明申请

US20110260333A1 INTERCONNECT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：半导体集成电路和包括其中的半导体器件的互连结构
公开(公告)号：US20110260333A1
公开(公告)日：2011-10-27
申请号：US13169398
申请日：2011-06-27
申请人： Yoichi MATSUMURA , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
发明人： Yoichi MATSUMURA , Chie Kabuo , Takako Ohashi , Tadafumi Kadota , Kazuhiko Fujimoto , Hirofumi Miyashita
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit chip including an interconnect layer in which there is a limitation on the lengths of interconnects or areas occupied by the interconnects, empty spaces between power supply interconnect segments having the same potential located in parallel to a priority interconnect direction, are shifted relative to each other within the limits of the lengths and areas of power supply interconnects. As a result, a local increase in resistance is dispersed, whereby an influence on a voltage drop is reduced.
摘要翻译：在具有互连层的互连层的互连层的半导体集成电路芯片中，互连的占用面积的区域有限制，具有与优先级互连方向平行的相同电位的电源互连区段之间的空位被移位在电源互连的长度和面积的限度内相对于彼此。结果，电阻的局部增加被分散，从而降低对电压降的影响。

3. 发明申请

US20070022400A1 Method, program, and apparatus for designing layout of semiconductor integrated circuit 审中-公开
标题翻译：用于设计半导体集成电路布局的方法，程序和设备
公开(公告)号：US20070022400A1
公开(公告)日：2007-01-25
申请号：US11436520
申请日：2006-05-19
申请人： Tadafumi Kadota
发明人： Tadafumi Kadota
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： In a method for designing a layout for an LSI, library data, which is information on a standard cell with an assigned parameter or parameters each indicating the probability of occurrence of violations of design rules at a pin connection point, is read into a library information read section in a global routing processing device. And in a global routing density processing section and a wire route determination processing section, the density of global routes that pass above a chip area divided into a plurality of portions in a grid pattern by a grid division processing section is set according to the parameters, so that the density of routes at pin connection points where the probability of occurrence of violations of design rules is high becomes low. Therefore, the global routing is carried out in such a manner that occurrence of violations of design rules at the pin connection points are prevented as much as possible.
摘要翻译：在设计LSI的布局的方法中，作为具有指定参数的标准单元的信息的图书馆数据或每个指示在引脚连接点处违反设计规则的概率的参数的库数据被读入库信息读取部分在全局路由处理设备中。并且在全局路由密度处理部分和有线路由决定处理部中，根据参数设定通过网格划分处理部分分割成网格图案的多个部分的芯片区域之上的全局路由的密度，使得违反设计规则的发生概率高的引脚连接点处的路由密度变低。因此，全局路由的执行方式是尽可能地防止在引脚连接点违反设计规则的发生。

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