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1. 发明授权

US07566586B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07566586B2
公开(公告)日：2009-07-28
申请号：US11634119
申请日：2006-12-06
申请人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Kimio Nakamura , Kuniko Ishikawa , Yukio Ozaki
发明人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Kimio Nakamura , Kuniko Ishikawa , Yukio Ozaki
IPC分类号： H01L21/00
CPC分类号： H01L21/563 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81205 , H01L2224/81801 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/00 , H01L2924/3512
摘要： A method of manufacturing a semiconductor device flip-chip bonds electrode terminals of a substrate and a semiconductor chip together by solid-phase diffusion and underfills a gap between the substrate and the semiconductor chip with a thermosetting resin without the bonds between the terminals breaking due to heat in an underfill hardening step. The method includes a bonding step of flip-chip bonding the electrode terminals of the substrate and the semiconductor chip by solid-phase diffusion, an underfill filling step of filling the gap between the substrate and the semiconductor chip with the underfill material, and the underfill hardening step where the underfill material is heated to the hardening temperature to harden the underfill material. During the underfill hardening step, a member with a lower coefficient of thermal expansion out of the substrate and the semiconductor chip is heated to a higher temperature than the other member.
摘要翻译：半导体器件倒装芯片的制造方法通过固相扩散将基板和半导体芯片的电极端子连接在一起，并且用热固性树脂对基板和半导体芯片之间的间隙进行底部填充，而不会由于端子断裂而导致端子之间的结合在底部填充硬化步骤中加热。该方法包括通过固相扩散将基板和半导体芯片的电极端子倒装连接的接合步骤，用底部填充材料填充基板和半导体芯片之间的间隙的底部填充步骤，以及底部填充硬化步骤，其中将底部填充材料加热至硬化温度以使底部填充材料硬化。在底部填充硬化工序中，将从基板和半导体芯片的热膨胀系数较低的部件加热到比其他部件高的温度。

2. 发明申请

US20070264752A1 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20070264752A1
公开(公告)日：2007-11-15
申请号：US11634119
申请日：2006-12-06
申请人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Kimio Nakamura , Kuniko Ishikawa , Yukio Ozaki
发明人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Kimio Nakamura , Kuniko Ishikawa , Yukio Ozaki
IPC分类号： H01L21/00
CPC分类号： H01L21/563 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81205 , H01L2224/81801 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/00 , H01L2924/3512
摘要： A method of manufacturing a semiconductor device flip-chip bonds electrode terminals of a substrate and a semiconductor chip together by solid-phase diffusion and underfills a gap between the substrate and the semiconductor chip with a thermosetting resin without the bonds between the terminals breaking due to heat in an underfill hardening step. The method includes a bonding step of flip-chip bonding the electrode terminals of the substrate and the semiconductor chip by solid-phase diffusion, an underfill filling step of filling the gap between the substrate and the semiconductor chip with the underfill material, and the underfill hardening step where the underfill material is heated to the hardening temperature to harden the underfill material. During the underfill hardening step, a member with a lower coefficient of thermal expansion out of the substrate and the semiconductor chip is heated to a higher temperature than the other member.
摘要翻译：半导体器件倒装芯片的制造方法通过固相扩散将基板和半导体芯片的电极端子连接在一起，并且用热固性树脂对基板和半导体芯片之间的间隙进行底部填充，而不会由于端子断裂而导致端子之间的结合在底部填充硬化步骤中加热。该方法包括通过固相扩散将基板和半导体芯片的电极端子倒装连接的接合步骤，用底部填充材料填充基板和半导体芯片之间的间隙的底部填充步骤，以及底部填充硬化步骤，其中将底部填充材料加热至硬化温度以使底部填充材料硬化。在底部填充硬化工序中，将从基板和半导体芯片的热膨胀系数较低的部件加热到比其他部件高的温度。

3. 发明授权

US07416921B2 Method for flip-chip mounting utilizing a delay curing-type adhesive with two-part hardening resin 有权
标题翻译：使用具有两部分硬化树脂的延迟固化型粘合剂进行倒装芯片安装的方法
公开(公告)号：US07416921B2
公开(公告)日：2008-08-26
申请号：US11066483
申请日：2005-02-28
申请人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Takayoshi Matsumura , Kimio Nakamura
发明人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Takayoshi Matsumura , Kimio Nakamura
IPC分类号： H01L21/00
CPC分类号： H01L21/563 , H01L24/29 , H01L24/75 , H01L24/81 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75 , H01L2224/75753 , H01L2224/81205 , H01L2224/81232 , H01L2224/81801 , H01L2224/83099 , H01L2224/83102 , H01L2224/83192 , H01L2224/83874 , H01L2224/92125 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01327 , H01L2924/07802 , H01L2924/19043 , Y10T156/10 , H01L2924/00 , H01L2224/0401
摘要： A method of flip-chip mounting a semiconductor chip can carry out bonding at normal temperature and improves the positional accuracy of bonding. The method of flip-chip bonding a semiconductor chip 52 includes a step of providing a hardening trigger that is not heat to insulating adhesive 51 either before the semiconductor chip 52 is mounted on the substrate 50 or during bonding; and a step of bonding the bumps of the semiconductor chip to the pads of the substrate 50 by pressure welding or metal combining while hardening of the insulating adhesive 51 is progressing due to provision of the hardening trigger.
摘要翻译：半导体芯片的倒装芯片的安装方法可以在常温下进行接合，提高接合的位置精度。半导体芯片52的倒装芯片接合的方法包括在将半导体芯片52安装在基板50上之前或在接合期间提供不加热以绝缘粘合剂51的硬化触发的步骤; 以及通过压力焊接或金属组合将半导体芯片的凸点接合到基板50的焊盘的步骤，同时绝缘粘合剂51的硬化由于设置硬化触发而正在进行。

4. 发明申请

US20060099809A1 Method of flip-chip mounting a semiconductor chip and mounting apparatus using the same 有权
标题翻译：半导体芯片的倒装芯片的安装方法及使用其的安装装置
公开(公告)号：US20060099809A1
公开(公告)日：2006-05-11
申请号：US11066483
申请日：2005-02-28
申请人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Takayoshi Matsumura , Kimio Nakamura
发明人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Takayoshi Matsumura , Kimio Nakamura
IPC分类号： H01L21/44
CPC分类号： H01L21/563 , H01L24/29 , H01L24/75 , H01L24/81 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75 , H01L2224/75753 , H01L2224/81205 , H01L2224/81232 , H01L2224/81801 , H01L2224/83099 , H01L2224/83102 , H01L2224/83192 , H01L2224/83874 , H01L2224/92125 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01327 , H01L2924/07802 , H01L2924/19043 , Y10T156/10 , H01L2924/00 , H01L2224/0401
摘要： A method of flip-chip mounting a semiconductor chip can carry out bonding at normal temperature and improves the positional accuracy of bonding. The method of flip-chip bonding a semiconductor chip 52 includes a step of providing a hardening trigger that is not heat to insulating adhesive 51 either before the semiconductor chip 52 is mounted on the substrate 50 or during bonding; and a step of bonding the bumps of the semiconductor chip to the pads of the substrate 50 by pressure welding or metal combining while hardening of the insulating adhesive 51 is progressing due to provision of the hardening trigger.
摘要翻译：半导体芯片的倒装芯片的安装方法可以在常温下进行接合，提高接合的位置精度。半导体芯片52的倒装芯片接合的方法包括在将半导体芯片52安装在基板50上之前或在接合期间提供不加热以绝缘粘合剂51的硬化触发的步骤; 以及通过压力焊接或金属组合将半导体芯片的凸点接合到基板50的焊盘的步骤，同时绝缘粘合剂51的硬化由于设置硬化触发而正在进行。

5. 发明申请

US20060097029A1 Method of flip-chip bonding 审中-公开
标题翻译：倒装芯片接合方法
公开(公告)号：US20060097029A1
公开(公告)日：2006-05-11
申请号：US11062959
申请日：2005-02-23
申请人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Takayoshi Matsumura , Yukio Ozaki
发明人： Norio Kainuma , Hidehiko Kira , Kenji Kobae , Takayoshi Matsumura , Yukio Ozaki
IPC分类号： B23K1/06
CPC分类号： B23K20/10 , B23K1/0016 , B23K2101/40
摘要： A method of flip-chip bonding can favorably activate the bonding surfaces and remove oxide films when bonding pads and bumps of a semiconductor chip and a substrate and avoids problems such as the bumps being excessively flattened and the bonds between connection terminals being destroyed by subsequent ultrasonic vibration. The method includes an aligning step 2 that aligns and places in contact bumps or pads of a semiconductor chip and pads or bumps of a substrate, a leveling step 4 that levels the shapes of the bumps by pressing together the semiconductor chip and the substrate with a first predetermined load, a bonding preparation step 6 that applies ultrasonic vibration to the semiconductor chip and/or the substrate so that the amplitude of the ultrasonic vibration gradually increases while the first predetermined load weakens, and a bonding step 8 that bonds the bumps and pads by applying ultrasonic vibration to the semiconductor chip and/or the substrate in a state where the semiconductor chip and the substrate are pressed together with a second predetermined load that is smaller than the first predetermined load.
摘要翻译：倒装芯片接合的方法可以有利地激活接合表面并且在接合半导体芯片和基板的焊盘和凸点时去除氧化膜，并且避免诸如凸块过度平坦的问题，并且连接端子之间的接合被随后的超声波破坏振动。该方法包括：对准步骤2，其对准和放置在半导体芯片的接触凸块或焊盘以及衬底的焊盘或凸块;调平步骤4，其通过将半导体芯片和衬底压在一起来调整凸块的形状第一预定负载，对半导体芯片和/或基板施加超声波振动的接合准备步骤6，使得当第一预定负载变弱时超声波振动的幅度逐渐增加;以及接合步骤8，其将凸块和焊盘通过在半导体芯片和基板以比第一预定负载小的第二预定负载被压在一起的状态下，向半导体芯片和/或基板施加超声波振动。

6. 发明申请

US20090146653A1 Slider tester 审中-公开
公开(公告)号：US20090146653A1
公开(公告)日：2009-06-11
申请号：US12292651
申请日：2008-11-24
申请人： Norio Kainuma , Kenji Kobae , Hidehiko Kira , Hiroshi Kobayashi , Shuichi Takeuchi , Takayoshi Matsumura , Hirokazu Yamanishi , Shinji Hiraoka , Yoshiaki Yanagida
发明人： Norio Kainuma , Kenji Kobae , Hidehiko Kira , Hiroshi Kobayashi , Shuichi Takeuchi , Takayoshi Matsumura , Hirokazu Yamanishi , Shinji Hiraoka , Yoshiaki Yanagida
IPC分类号： G01R33/12
CPC分类号： G11B5/455 , G11B5/4555 , G11B5/6005 , H01R13/2421 , H01R2201/20
摘要： A slider tester includes a driving unit that rotates a test medium, a set plate that detachably supports a slider as a single body, and an investigating apparatus that is electrically connected to the slider supported by the set plate and investigates the characteristics of the slider. A movable support part 30 that tiltably supports the slider is provided on the set plate. There is also provided a pressing mechanism that elastically presses the slider via the movable support part toward a surface of the medium to dispose the slider floating over the surface of the medium. The pressing mechanism includes an elastic body 56 composed of a plate spring that contacts the movable support part and elastically presses the movable support part.

7. 发明授权

US07394163B2 Method of mounting semiconductor chip 失效
标题翻译：安装半导体芯片的方法
公开(公告)号：US07394163B2
公开(公告)日：2008-07-01
申请号：US10187843
申请日：2002-07-03
申请人： Shunji Baba , Takatoyo Yamakami , Norio Kainuma , Kenji Kobae , Hidehiko Kira , Hiroshi Kobayashi
发明人： Shunji Baba , Takatoyo Yamakami , Norio Kainuma , Kenji Kobae , Hidehiko Kira , Hiroshi Kobayashi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/563 , H01L21/67092 , H01L21/67144 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/81 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/1134 , H01L2224/13144 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/75 , H01L2224/75743 , H01L2224/81191 , H01L2224/81205 , H01L2224/81801 , H01L2224/83192 , H01L2224/83859 , H01L2224/83862 , H01L2224/83868 , H01L2224/83874 , H01L2224/83885 , H01L2224/83951 , H01L2224/85444 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2224/05599
摘要： A method of mounting a semiconductor chip in which an IC chip is mounted by filling a gap between the chip and a substrate with adhesive which functions as an underfill. The fillet of the underfill is made to have a preferable shape. To accomplish this, a head IC chip provided with bumps is placed on a suspension that is covered with the underfill adhesive and is provided with pads. A bonding tool presses the head IC chip and applies ultrasonic oscillation to the head IC chip, so that the bumps are properly bonded to the pads. When the head IC chip is pressed and subjected to ultrasonic oscillation, the ultraviolet rays 108 are emitted so as to harden the peripheral portion 151a of the adhesive 151 spread out between the head IC chip 11 and the suspension 12.
摘要翻译：通过用作底层填充剂的粘合剂填充芯片和基板之间的间隙来安装半导体芯片的方法，其中安装IC芯片。底部填充物的圆角被制成具有优选的形状。为了实现这一点，将具有凸块的头IC芯片放置在被底部填充胶粘剂覆盖的悬挂上，并设置有垫。接合工具按压头IC芯片并对头IC芯片施加超声波振荡，使得凸块适当地粘合到焊盘。当头部IC芯片被按压并进行超声波振荡时，发射紫外线108以使在头IC芯片11和悬架12之间展开的粘合剂151的周边部分151a硬化。

8. 发明授权

US07347347B2 Head assembly, disk unit, and bonding method and apparatus 失效
标题翻译：头部组件，磁盘单元，接合方法和装置
公开(公告)号：US07347347B2
公开(公告)日：2008-03-25
申请号：US10972440
申请日：2004-10-26
申请人： Hidehiko Kira , Shunji Baba , Norio Kainuma , Toru Okada , Takatoyo Yamakami , Yasunori Sasaki , Takeshi Komiyama , Kenji Kobae , Hiroshi Kobayashi
发明人： Hidehiko Kira , Shunji Baba , Norio Kainuma , Toru Okada , Takatoyo Yamakami , Yasunori Sasaki , Takeshi Komiyama , Kenji Kobae , Hiroshi Kobayashi
IPC分类号： B23K1/06 , B23K37/00
CPC分类号： H01L21/568 , B29C2043/5825 , G11B5/4806 , G11B5/486 , H01L21/56 , H01L21/563 , H01L21/6835 , H01L23/3107 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/75 , H01L24/81 , H01L24/94 , H01L29/0657 , H01L2223/54426 , H01L2223/5448 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/1134 , H01L2224/11822 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/274 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/45144 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/749 , H01L2224/75 , H01L2224/7515 , H01L2224/75302 , H01L2224/7565 , H01L2224/75745 , H01L2224/75753 , H01L2224/81801 , H01L2224/83194 , H01L2224/83856 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01068 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/10158 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2224/13111
摘要： A head assembly is provided with a mounting surface, and an integrated circuit chip which is mounted on the mounting surface and processes signals. The integrated circuit chip is covered by a layer which prevents generation of foreign particles from the integrated circuit chip by the provision of the layer.
摘要翻译：头组件设置有安装表面，以及安装在安装表面上并处理信号的集成电路芯片。集成电路芯片由防止由集成电路芯片产生异物的层所覆盖。

9. 发明申请

US20050196529A1 Resin coating method and apparatus 审中-公开
公开(公告)号：US20050196529A1
公开(公告)日：2005-09-08
申请号：US11117307
申请日：2005-04-29
申请人： Shunji Baba , Takatoyo Yamakami , Norio Kainuma , Kenji Kobae , Hidehiko Kira , Hiroshi Kobayashi
发明人： Shunji Baba , Takatoyo Yamakami , Norio Kainuma , Kenji Kobae , Hidehiko Kira , Hiroshi Kobayashi
IPC分类号： G03F7/16 , B05C5/02 , B05C11/10 , B05D3/00 , B05D7/00 , H01L21/56 , H01L21/60 , H05K1/02 , H05K3/00 , H05K3/28 , B05D5/12
CPC分类号： B05C11/1034 , B05C5/0212 , H01L21/563 , H01L24/743 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/83192 , H01L2924/00014 , H05K1/0269 , H05K3/0091 , H05K3/284 , H05K2203/0126 , H05K2203/163 , H01L2924/00 , H01L2224/05599
摘要： A resin coating method for applying resin to a predetermined region of a wiring board includes the steps of imaging an external appearance of the resin extruded from a resin application device; and automatically adjusting an amount of the resin extruded from the resin application device based on the external appearance of the resin obtained in the imaging step.

10. 发明申请

US20050057856A1 Head assembly, disk unit, and bonding method and apparatus 失效
标题翻译：头部组件，磁盘单元，接合方法和装置
公开(公告)号：US20050057856A1
公开(公告)日：2005-03-17
申请号：US10972440
申请日：2004-10-26
申请人： Hidehiko Kira , Shunji Baba , Norio Kainuma , Toru Okada , Takatoyo Yamakami , Yasunori Sasaki , Takeshi Komiyama , Kenji Kobae , Hiroshi Kobayashi
发明人： Hidehiko Kira , Shunji Baba , Norio Kainuma , Toru Okada , Takatoyo Yamakami , Yasunori Sasaki , Takeshi Komiyama , Kenji Kobae , Hiroshi Kobayashi
IPC分类号： G11B5/48 , H01L21/56 , H01L21/60 , H01L21/68 , H01L23/31 , H01L29/06 , G11B21/20
CPC分类号： H01L21/568 , B29C2043/5825 , G11B5/4806 , G11B5/486 , H01L21/56 , H01L21/563 , H01L21/6835 , H01L23/3107 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/75 , H01L24/81 , H01L24/94 , H01L29/0657 , H01L2223/54426 , H01L2223/5448 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/1134 , H01L2224/11822 , H01L2224/13099 , H01L2224/13144 , H01L2224/16225 , H01L2224/274 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/45144 , H01L2224/73104 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/749 , H01L2224/75 , H01L2224/7515 , H01L2224/75302 , H01L2224/7565 , H01L2224/75745 , H01L2224/75753 , H01L2224/81801 , H01L2224/83194 , H01L2224/83856 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01068 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/10158 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2224/13111
摘要： A head assembly is provided with a mounting surface, and an integrated circuit chip which is mounted on the mounting surface and processes signals. The integrated circuit chip is covered by a layer which prevents generation of foreign particles from the integrated circuit chip by the provision of the layer.
摘要翻译：头组件设置有安装表面，以及安装在安装表面上并处理信号的集成电路芯片。集成电路芯片由防止由集成电路芯片产生异物的层所覆盖。

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