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1. 发明授权

US08324925B2 Output buffer circuit and differential output buffer circuit, and transmission method 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及其传输方式
公开(公告)号：US08324925B2
公开(公告)日：2012-12-04
申请号：US13106926
申请日：2011-05-13
申请人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003
CPC分类号： H03K19/018521
摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.
摘要翻译：输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

2. 发明申请

US20090003463A1 OUTPUT BUFFER CIRCUIT, SIGNAL TRANSMISSION INTERFACE CIRCUIT AND APPARATUS 审中-公开
标题翻译：输出缓冲电路，信号传输接口电路和设备
公开(公告)号：US20090003463A1
公开(公告)日：2009-01-01
申请号：US12099953
申请日：2008-04-09
申请人： Satoshi Muraoka , Norio Chujo
发明人： Satoshi Muraoka , Norio Chujo
IPC分类号： H04B3/00 , H03K19/0175
CPC分类号： H03K19/0005 , H03K17/164 , H03K19/018521 , H04L25/0288 , H04L25/03343
摘要： An output buffer circuit which transmits a logic signal to a transmission line includes a transmission pre-emphasis output circuit and a transmission pre-emphasis amount determination circuit. The transmission pre-emphasis output circuit controls a pre-emphasis amount according to an output signal from the transmission pre-emphasis amount determination circuit. The transmission pre-emphasis amount determination circuit adjusts a pre-emphasis amount and the number of pre-emphasis taps according to a pseudo loss control signal, controls a pre-emphasis amount of a transmission signal so that a signal amplitude is made smaller in a signal component with a high frequency than that of a signal component with a low frequency, and imparts signal degradation to a received waveform to realize transmission loss in a pseudo manner.
摘要翻译：向传输线发送逻辑信号的输出缓冲电路包括发送预加重输出电路和发送预加重量确定电路。发送预加重输出电路根据来自发送预加重量确定电路的输出信号来控制预加重量。发送预加重量确定电路根据伪损失控制信号调整预加重量和预加重抽头的数量，控制发送信号的预加重量，使信号幅度变小信号分量高于具有低频率的信号分量的信号分量，并且对接收到的波形施加信号劣化，以伪方式实现传输损耗。

3. 发明申请

US20080030242A1 DIFFERENTIAL SIGNALING SYSTEM AND METHOD OF CONTROLLING SKEW BETWEEN SIGNAL LINES THEREOF 有权
标题翻译：差分信号系统及其信号线控制方法
公开(公告)号：US20080030242A1
公开(公告)日：2008-02-07
申请号：US11831087
申请日：2007-07-31
申请人： Norio Chujo , Satoshi Muraoka
发明人： Norio Chujo , Satoshi Muraoka
IPC分类号： H03K3/00 , H01R13/66 , H03K5/12
CPC分类号： H04L25/0272 , H01L24/45 , H01L24/46 , H01L2224/45565 , H01L2224/45572 , H01L2224/48092 , H01L2224/48137 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/43 , H01L2924/01006
摘要： The present invention provides a differential signaling system comprising: a driver circuit that transmits a differential signal; a receiver circuit that receives the differential signal; and two or more signal lines used for the differential signal to be transmitted by the driver circuit and received by the receiver circuit, wherein the driver circuit gives an arbitrary time lag between the two signals that form the differential signal before transmitting them.
摘要翻译：本发明提供一种差分信号系统，包括：发送差分信号的驱动电路; 接收差分信号的接收机电路; 并且用于差分信号的两条或更多条信号线由驱动器电路传输并由接收器电路接收，其中驱动器电路在发送差分信号之前形成差分信号的两个信号之间给出任意时滞。

4. 发明申请

US20110215830A1 OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及传输方式
公开(公告)号：US20110215830A1
公开(公告)日：2011-09-08
申请号：US13106926
申请日：2011-05-13
申请人： Satoshi MURAOKA , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi MURAOKA , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003
CPC分类号： H03K19/018521
摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.
摘要翻译：输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

5. 发明申请

US20100219856A1 OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及传输方式
公开(公告)号：US20100219856A1
公开(公告)日：2010-09-02
申请号：US12716796
申请日：2010-03-03
申请人： Satoshi MURAOKA , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi MURAOKA , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003 , H03K19/094
CPC分类号： H03K19/018521
摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.
摘要翻译：在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个选择器逻辑的选择信号。

6. 发明授权

US07969197B2 Output buffer circuit and differential output buffer circuit, and transmission method 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及其传输方式
公开(公告)号：US07969197B2
公开(公告)日：2011-06-28
申请号：US12716796
申请日：2010-03-03
申请人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.
摘要翻译：输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

7. 发明申请

US20080265944A1 Output Buffer Circuit and Differential Output Buffer Circuit, and Transmission Method 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及传输方式
公开(公告)号：US20080265944A1
公开(公告)日：2008-10-30
申请号：US11686560
申请日：2007-03-15
申请人： SATOSHI MURAOKA , Norio Chujo , Ritsuro Orihashi
发明人： SATOSHI MURAOKA , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018521
摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.
摘要翻译：在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个选择器逻辑的选择信号。

8. 发明授权

US07786751B2 Differential signaling system and method of controlling skew between signal lines thereof 有权
标题翻译：差分信号系统及其信号线之间的偏斜控制方法
公开(公告)号：US07786751B2
公开(公告)日：2010-08-31
申请号：US11831087
申请日：2007-07-31
申请人： Norio Chujo , Satoshi Muraoka
发明人： Norio Chujo , Satoshi Muraoka
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0272 , H01L24/45 , H01L24/46 , H01L2224/45565 , H01L2224/45572 , H01L2224/48092 , H01L2224/48137 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/43 , H01L2924/01006
摘要： The present invention provides a differential signaling system comprising: a driver circuit that transmits a differential signal; a receiver circuit that receives the differential signal; and two or more signal lines used for the differential signal to be transmitted by the driver circuit and received by the receiver circuit, wherein the driver circuit gives an arbitrary time lag between the two signals that form the differential signal before transmitting them.
摘要翻译：本发明提供一种差分信号系统，包括：发送差分信号的驱动电路; 接收差分信号的接收机电路; 并且用于差分信号的两条或更多条信号线由驱动器电路传输并由接收器电路接收，其中驱动器电路在发送差分信号之前形成差分信号的两个信号之间给出任意时滞。

9. 发明授权

US07692445B2 Output buffer circuit and differential output buffer circuit, and transmission method 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及其传输方式
公开(公告)号：US07692445B2
公开(公告)日：2010-04-06
申请号：US11686560
申请日：2007-03-15
申请人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/003
CPC分类号： H03K19/018521
摘要： In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.
摘要翻译：在包括变频器1至变频器3的输出缓冲电路中，延迟电路1至延迟电路3用于将输入信号延迟特定时间，缓冲器1至缓冲器3，以及用于将逻辑信号发送到传输路径的功能在传输路径中具有一定量的信号衰减，在发送侧产生包括四种或更多种信号电压的波形，使预加重量变为可变，并使缓冲器的导通电阻Rs保持恒定。选择器电路1至选择器电路3位于缓冲器之前，反相器能够通过选择器逻辑选择要输入到缓冲器的信号，反转数据信号，并且预加重量和预加重数量通过一个选择器逻辑的选择信号。

10. 发明授权

US09698783B2 Driver integrated circuit 有权
公开(公告)号：US09698783B2
公开(公告)日：2017-07-04
申请号：US14122623
申请日：2012-05-24
申请人： Wen Li , Norio Chujo , Masami Makuuchi , Takehito Kamimura
发明人： Wen Li , Norio Chujo , Masami Makuuchi , Takehito Kamimura
IPC分类号： H03K19/0175 , H03F1/52 , H03F3/195 , H03F3/21 , H03F3/30
CPC分类号： H03K19/0175 , H01L2224/48137 , H01L2924/181 , H03F1/52 , H03F3/195 , H03F3/211 , H03F3/3022 , H03F2200/189 , H03K19/017509 , H01L2924/00012
摘要： Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).

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