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1. 发明申请

US20060291305A1 Semiconductor device and program data redundancy method therefor 有权
标题翻译：半导体器件及其程序数据冗余方法
公开(公告)号：US20060291305A1
公开(公告)日：2006-12-28
申请号：US11444251
申请日：2006-05-30
申请人： Norikatsu Suzuki , Makoto Niimi , Satoru Kawmoto
发明人： Norikatsu Suzuki , Makoto Niimi , Satoru Kawmoto
IPC分类号： G11C29/00
CPC分类号： G11C29/76
摘要： A semiconductor device (1) is provided which includes a regular cell array unit (30), a redundant cell array unit (31) that is provided in relation to the regular cell array unit (30), and a PGM/ER state machine (20) that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S3), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S8) into the redundant cell array unit (31). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (31), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.
摘要翻译：提供一种半导体器件（1），其包括正常单元阵列单元（30），相对于正常单元阵列单元（30）提供的冗余单元阵列单元（31）和PGM / ER状态机 20），其控制重编程，其中当正规单元阵列单元中的扇区的编程失败时（步骤S 3），写入编程失败的数据和已经存储在正常单元阵列单元中的扇区中的数据被写入（步骤 S 8）插入到冗余单元阵列单元（31）中。由于执行重编程以将已经写入扇区的数据以及编程中涉及的数据写入冗余单元阵列单元（31），所以可以防止数据丢失并且可以确保数据的可靠性系统。

2. 发明授权

US07739559B2 Semiconductor device and program data redundancy method therefor 有权
标题翻译：半导体器件及其程序数据冗余方法
公开(公告)号：US07739559B2
公开(公告)日：2010-06-15
申请号：US11444251
申请日：2006-05-30
申请人： Norikatsu Suzuki , Makoto Niimi , Satoru Kawamoto
发明人： Norikatsu Suzuki , Makoto Niimi , Satoru Kawamoto
IPC分类号： G11C29/00
CPC分类号： G11C29/76
摘要： A semiconductor device (1) is provided which includes a regular cell array unit (30), a redundant cell array unit (31) that is provided in relation to the regular cell array unit (30), and a PGM/ER state machine (20) that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S3), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S8) into the redundant cell array unit (31). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (31), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.
摘要翻译：提供一种半导体器件（1），其包括正常单元阵列单元（30），相对于正常单元阵列单元（30）提供的冗余单元阵列单元（31）和PGM / ER状态机 20），其中当编程正常单元阵列单元中的扇区失败时（步骤S3），写入失败的编程中涉及的数据和已经存储在常规单元阵列单元中的扇区中的数据被写入（步骤S8 ）到冗余单元阵列单元（31）中。由于执行重编程以将已经写入扇区的数据以及编程中涉及的数据写入冗余单元阵列单元（31），所以可以防止数据丢失并且可以确保数据的可靠性系统。

3. 发明授权

US07889573B2 Time reduction of address setup/hold time for semiconductor memory 有权
标题翻译：减少半导体存储器的地址设置/保持时间
公开(公告)号：US07889573B2
公开(公告)日：2011-02-15
申请号：US12341886
申请日：2008-12-22
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
摘要翻译：在本发明的存储装置中，响应于锁存控制信号对一系列信号进行锁存控制。设置锁存控制信号的锁存控制端子和分别输入一系列信号的多个信号端子。这里，分别提供多个锁存电路以对应于多个信号端子。多个锁存电路分别位于与其相关联的信号端子规定距离内并且距离锁存器控制端子在指定距离内。从信号端子到其相关联的锁存电路的信号传输的延迟可以被均衡，并且来自锁存控制端子的信号传输的延迟被输入到锁存电路，锁存控制端子用于执行锁存控制的信号被输入到锁存电路。这有助于减少信号的锁存特性的偏移。

4. 发明授权

US5731720A Semiconductor integrated circuit device capable of reducing power consumption 失效
标题翻译：半导体集成电路器件能够降低功耗
公开(公告)号：US5731720A
公开(公告)日：1998-03-24
申请号：US784539
申请日：1997-01-21
申请人： Takaaki Suzuki , Makoto Niimi , Hideaki Kawai , Masato Kaida
发明人： Takaaki Suzuki , Makoto Niimi , Hideaki Kawai , Masato Kaida
IPC分类号： G11C11/401 , G11C11/407 , H01L21/822 , H01L27/04 , H01L27/10 , H03K19/00 , H03K17/30
CPC分类号： H03K19/0013
摘要： A semiconductor integrated circuit device is intended to prevent generation of an unnecessary leak current and hence to reduce power consumption. In the semiconductor integrated circuit device comprising: a current path which is formed between a predetermined power source terminal (or a predetermined power source pad) and a predetermined low potential power source line, a comparison circuit for comparing a node potential in the current path with a predetermined threshold voltage to thereby detect whether the voltage applied to said power source terminal is a voltage which is larger than an upper limit value of the terminal voltage, a signal generation circuit for generating a predetermined logic signal when the states of some designated control terminals satisfy a combination which is determined in advance, if the logic state of an output signal of said signal generation circuit is a predetermined logic state when said comparison circuit has detected that the voltage applied to the power source terminal is a voltage which is larger than an upper limit value of the terminal voltage, a circuit equipped with a predetermined function mounted on the chip is activated, the semiconductor integrated circuit device being characterized by comprising ON/OFF circuit for turning on and off said current path in accordance with the logic state of the output signal of said signal generation circuit.
摘要翻译：半导体集成电路器件旨在防止不必要的泄漏电流的产生，从而降低功耗。在半导体集成电路装置中，包括：形成在预定电源端子（或预定电源焊盘）和预定低电位电源线之间的电流路径，用于将当前路径中的节点电位与预定的阈值电压，从而检测施加到所述电源端子的电压是否是大于端子电压的上限值的电压;当一些指定的控制端子的状态产生预定逻辑信号的信号产生电路如果所述信号发生电路的输出信号的逻辑状态是预定的逻辑状态，当所述比较电路检测到施加到电源端子的电压是大于电源端的电压时，满足预先确定的组合端子电压的上限值，配备有预定功能的电路 n的半导体集成电路装置的特征在于包括根据所述信号发生电路的输出信号的逻辑状态接通和断开所述电流路径的ON / OFF电路。

5. 发明授权

US07808808B2 Nonvolatile memory device having a plurality of memory blocks 有权
标题翻译：具有多个存储块的非易失性存储器件
公开(公告)号：US07808808B2
公开(公告)日：2010-10-05
申请号：US12177039
申请日：2008-07-21
申请人： Takaaki Furuyama , Makoto Niimi , Masahiro Niimi
发明人： Takaaki Furuyama , Makoto Niimi , Masahiro Niimi
IPC分类号： G11C16/04
CPC分类号： G11C16/12
摘要： A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.
摘要翻译：提供一种能够防止读取操作和重写操作之间的干扰并且能够防止在存储器块之间同时执行读取操作和重写操作的情况下可能发生的故障的非易失性存储器件1。非易失性存储器件1设有多个存储体，重写控制单元2，第一电源线VCC1和第一接地线VSS1连接到该重写控制单元2，并且其适于控制相对于存储体i的重写操作，以及连接有第二电源线VCC2和第二接地线VSS2并且适于控制相对于存储体j的读取操作的读取控制单元5，其中重写控制单元2和读取控制单元5 被布置成彼此间隔开。

6. 发明授权

US08031537B2 Time reduction of address setup/hold time for semiconductor memory 有权
公开(公告)号：US08031537B2
公开(公告)日：2011-10-04
申请号：US12987466
申请日：2011-01-10
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

7. 发明授权

US06925005B2 AC sensing method memory circuit 失效
标题翻译：交流感测方式存储电路
公开(公告)号：US06925005B2
公开(公告)日：2005-08-02
申请号：US10647441
申请日：2003-08-26
申请人： Shoichi Kawamura , Masaru Yano , Makoto Niimi , Kenji Nagai
发明人： Shoichi Kawamura , Masaru Yano , Makoto Niimi , Kenji Nagai
IPC分类号： G11C16/06 , G11C5/00 , G11C16/04 , G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/3436
摘要： The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.
摘要翻译：本发明是一种存储器电路，包括：存储单元阵列，包括多个位线，多个字线以及设置在位线和字线之间的交叉位置的多个存储单元; 以及页缓冲器，其连接到位线，并且通过根据所选择的存储器的单元电流在预充电位线电位被放电时，用预定的感测定时判断位线的电位来检测存储单元数据细胞。此外，感测定时根据存储单元阵列中所选存储单元的位置而不同。

8. 发明授权

US08094478B2 Nonvolatile memory device having a plurality of memory blocks 有权
标题翻译：具有多个存储块的非易失性存储器件
公开(公告)号：US08094478B2
公开(公告)日：2012-01-10
申请号：US12878656
申请日：2010-09-09
申请人： Takaaki Furuyama , Makoto Niimi , Masahiro Niimi
发明人： Takaaki Furuyama , Makoto Niimi , Masahiro Niimi
IPC分类号： G11C5/06
CPC分类号： G11C16/12
摘要： A nonvolatile memory device 1 capable of preventing interference between a read operation and a rewrite operation, and capable of preventing malfunctions that may occur in the event the read operation and the rewrite operation are performed simultaneously between memory blocks is provided. The nonvolatile memory device 1 is provided with a plurality of banks, a rewrite control unit 2 to which a first power source line VCC1 and a first ground line VSS1 are connected and which is adapted to control a rewrite operation with respect to a bank i, and a read control unit 5 to which a second power source line VCC2 and a second ground line VSS2 are connected and which is adapted to control a read operation with respect to a bank j, wherein the rewrite control unit 2 and the read control unit 5 are arranged so as to be spaced from each another.
摘要翻译：提供一种能够防止读取操作和重写操作之间的干扰并且能够防止在存储器块之间同时执行读取操作和重写操作的情况下可能发生的故障的非易失性存储器件1。非易失性存储器件1设有多个存储体，重写控制单元2，第一电源线VCC1和第一接地线VSS1连接到该重写控制单元2，并且其适于控制相对于存储体i的重写操作，以及连接有第二电源线VCC2和第二接地线VSS2并且适于控制相对于存储体j的读取操作的读取控制单元5，其中重写控制单元2和读取控制单元5 被布置成彼此间隔开。

9. 发明申请

US20090323435A1 TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY 有权
标题翻译：减少半导体存储器的地址设置/保持时间
公开(公告)号：US20090323435A1
公开(公告)日：2009-12-31
申请号：US12341886
申请日：2008-12-22
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
摘要翻译：在本发明的存储装置中，响应于锁存控制信号对一系列信号进行锁存控制。设置锁存控制信号的锁存控制端子和分别输入一系列信号的多个信号端子。这里，分别提供多个锁存电路以对应于多个信号端子。多个锁存电路分别位于与其相关联的信号端子规定距离内并且距离锁存器控制端子在指定距离内。从信号端子到其相关联的锁存电路的信号传输的延迟可以被均衡，并且来自锁存控制端子的信号传输的延迟被输入到锁存电路，锁存控制端子用于执行锁存控制的信号被输入到锁存电路。这有助于减少信号的锁存特性的偏移。

10. 发明授权

US06658517B1 Communication controlling apparatus and serial bus managing apparatus 失效
标题翻译：通信控制装置和串行总线管理装置
公开(公告)号：US06658517B1
公开(公告)日：2003-12-02
申请号：US09613630
申请日：2000-07-11
申请人： Makoto Niimi , Tatsuo Bando
发明人： Makoto Niimi , Tatsuo Bando
IPC分类号： G06F1300
CPC分类号： H04N1/00127 , H04N1/00204 , H04N1/00347 , H04N2201/0015 , H04N2201/0039 , H04N2201/0044 , H04N2201/0049 , H04N2201/0081 , H04N2201/0082 , H04N2201/0084 , H04N2201/0093
摘要： A communication controlling apparatus, which is connected to a telephone line and a serial bus, comprises a mapping table, which brings a fixed address, which a terminal device possesses, into correspondence with a node ID assigned to a terminal device connected to the current serial bus. Then, the node ID of the terminal device, serving as a recipient of data received from the telephone line, is obtained from the mapping table, and the received data from the line is transmitted to the terminal device via the serial bus using the obtained node ID.
摘要翻译：连接到电话线和串行总线的通信控制装置包括映射表，其将终端设备拥有的固定地址与分配给连接到当前串行端口的终端设备的节点ID相对应总线。然后，从映射表中获取作为从电话线接收的数据的接收者的终端设备的节点ID，并且通过串行总线将来自线路的接收数据通过串行总线发送到终端设备 ID。

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