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1. 发明授权

US06925005B2 AC sensing method memory circuit 失效
标题翻译：交流感测方式存储电路
公开(公告)号：US06925005B2
公开(公告)日：2005-08-02
申请号：US10647441
申请日：2003-08-26
申请人： Shoichi Kawamura , Masaru Yano , Makoto Niimi , Kenji Nagai
发明人： Shoichi Kawamura , Masaru Yano , Makoto Niimi , Kenji Nagai
IPC分类号： G11C16/06 , G11C5/00 , G11C16/04 , G11C16/26 , G11C16/34
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/3436
摘要： The present invention is a memory circuit, comprises: a memory cell array including a plurality of bit lines, a plurality of word lines, and a plurality of memory cells disposed in the positions of intersection between the bit lines and the word lines; and a page buffer, which is connected to the bit line and which detects memory cell data by judging with predetermined sense timing the potential of the bit line when a pre-charged bit line potential is discharged in accordance to a cell current of a selected memory cell. Further the sense timing differs in accordance with the position of the selected memory cell in the memory cell array.
摘要翻译：本发明是一种存储器电路，包括：存储单元阵列，包括多个位线，多个字线以及设置在位线和字线之间的交叉位置的多个存储单元; 以及页缓冲器，其连接到位线，并且通过根据所选择的存储器的单元电流在预充电位线电位被放电时，用预定的感测定时判断位线的电位来检测存储单元数据细胞。此外，感测定时根据存储单元阵列中所选存储单元的位置而不同。

2. 发明申请

US20090323435A1 TIME REDUCTION OF ADDRESS SETUP/HOLD TIME FOR SEMICONDUCTOR MEMORY 有权
标题翻译：减少半导体存储器的地址设置/保持时间
公开(公告)号：US20090323435A1
公开(公告)日：2009-12-31
申请号：US12341886
申请日：2008-12-22
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
摘要翻译：在本发明的存储装置中，响应于锁存控制信号对一系列信号进行锁存控制。设置锁存控制信号的锁存控制端子和分别输入一系列信号的多个信号端子。这里，分别提供多个锁存电路以对应于多个信号端子。多个锁存电路分别位于与其相关联的信号端子规定距离内并且距离锁存器控制端子在指定距离内。从信号端子到其相关联的锁存电路的信号传输的延迟可以被均衡，并且来自锁存控制端子的信号传输的延迟被输入到锁存电路，锁存控制端子用于执行锁存控制的信号被输入到锁存电路。这有助于减少信号的锁存特性的偏移。

3. 发明授权

US07889573B2 Time reduction of address setup/hold time for semiconductor memory 有权
标题翻译：减少半导体存储器的地址设置/保持时间
公开(公告)号：US07889573B2
公开(公告)日：2011-02-15
申请号：US12341886
申请日：2008-12-22
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
摘要翻译：在本发明的存储装置中，响应于锁存控制信号对一系列信号进行锁存控制。设置锁存控制信号的锁存控制端子和分别输入一系列信号的多个信号端子。这里，分别提供多个锁存电路以对应于多个信号端子。多个锁存电路分别位于与其相关联的信号端子规定距离内并且距离锁存器控制端子在指定距离内。从信号端子到其相关联的锁存电路的信号传输的延迟可以被均衡，并且来自锁存控制端子的信号传输的延迟被输入到锁存电路，锁存控制端子用于执行锁存控制的信号被输入到锁存电路。这有助于减少信号的锁存特性的偏移。

4. 发明授权

US08031537B2 Time reduction of address setup/hold time for semiconductor memory 有权
公开(公告)号：US08031537B2
公开(公告)日：2011-10-04
申请号：US12987466
申请日：2011-01-10
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

5. 发明授权

US07821842B2 Synchronous memory devices and control methods for performing burst write operations 有权
标题翻译：同步存储器件和用于执行突发写入操作的控制方法
公开(公告)号：US07821842B2
公开(公告)日：2010-10-26
申请号：US12176997
申请日：2008-07-21
申请人： Kenji Nagai
发明人： Kenji Nagai
IPC分类号： G11C7/10
CPC分类号： G11C7/1018 , G11C7/1078 , G11C7/109
摘要： Synchronous memory devices and control methods for performing burst write operations are disclosed. In one embodiment, a synchronous memory device for controlling a burst write operation comprises a first buffer circuit for buffering a first control signal requesting an exit from the burst write operation in synchronization with a clock signal associated with the burst write operation, and a latch circuit for performing a reset in response to the first control signal forwarded by the first buffer circuit, wherein the reset triggers the exit from the burst write operation.
摘要翻译：公开了用于执行突发写入操作的同步存储器件和控制方法。在一个实施例中，用于控制突发写入操作的同步存储器装置包括：第一缓冲器电路，用于与与突发写入操作相关联的时钟信号同步地缓冲请求从突发写入操作退出的第一控制信号;以及锁存电路用于响应于由第一缓冲电路转发的第一控制信号执行复位，其中复位触发从突发写入操作的退出。

6. 发明申请

US20070047342A1 Storage device and control method of storage device 有权
标题翻译：存储设备的存储设备和控制方法
公开(公告)号：US20070047342A1
公开(公告)日：2007-03-01
申请号：US11510077
申请日：2006-08-25
申请人： Kenji Nagai
发明人： Kenji Nagai
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： In a storage device having a redundancy remedy function in a block unit having a memory cells array divided in plural blocks, prior to the access operation to individual memory cells in the block, the block address BA for specifying a block is entered, and block redundancy is determined in the entered block address BA, and hence it is not necessary to determine input or redundancy of the block address BA on every occasion of the access operation. As a result, the time to the access operation start to the memory cell can be shortened, and the access speed is enhanced.
摘要翻译：在具有在多个块中划分的存储单元阵列的块单元中具有冗余补救功能的存储设备中，在对块内的各个存储单元的访问操作之前，输入用于指定块的块地址BA，并且块冗余在输入的块地址BA中确定，因此不需要在访问操作的每个场合确定块地址BA的输入或冗余。结果，可以缩短开始到存储单元的访问操作的时间，并且提高访问速度。

7. 发明授权

US06633102B2 Insulator for armature of dynamo-electric machine 有权
标题翻译：发电机电枢绝缘子
公开(公告)号：US06633102B2
公开(公告)日：2003-10-14
申请号：US10064927
申请日：2002-08-29
申请人： Kenji Nagai , Hiroaki Kondo , Hisanobu Higashi , Takahiro Matsumoto
发明人： Kenji Nagai , Hiroaki Kondo , Hisanobu Higashi , Takahiro Matsumoto
IPC分类号： H02K104
CPC分类号： H02K3/38
摘要： An armature for a rotating electrical machine and more particularly to an insulating cover for the pole teeth around which the windings are formed that has good strength against the winding without risk of damage of the insulator due to increased thickness in the highly stressed areas.
摘要翻译：更具体地说，涉及一种用于旋转电机的电枢，更具体地说，涉及一种用于极齿的绝缘盖，绕组绕其形成，其具有对绕组的良好强度，而不会由于高应力区域中的厚度增加而导致绝缘体损坏的风险。 PTEXT>

8. 发明授权

US06420883B1 Semiconductor integrated circuit device and IC card 失效
标题翻译：半导体集成电路器件和IC卡
公开(公告)号：US06420883B1
公开(公告)日：2002-07-16
申请号：US09427594
申请日：1999-10-27
申请人： Kazuki Watanabe , Ryouzou Yoshino , Kenji Nagai , Tatsuya Nishihara
发明人： Kazuki Watanabe , Ryouzou Yoshino , Kenji Nagai , Tatsuya Nishihara
IPC分类号： G01R2708
CPC分类号： G06K19/0716 , G06K19/073 , G06K19/07728 , H01L27/0802
摘要： A semiconductor integrated circuit device provided with an IC chip so as to prevent its circuits from malfunction when the IC chip is cracked. To detect chip cracks, a resistor R01 is disposed at the outer periphery of the area which wants to detect the chip crack. If the chip is cracked and the resistance value of the resistor R01 is changed, the resistance change is detected, thereby controlling internal signals such as the power on reset signal and stopping the whole operation of the circuit device so as to prevent the circuits from malfunction. Thus, the system security can also be improved.
摘要翻译：具有IC芯片的半导体集成电路装置，以防止IC芯片破裂时其电路发生故障。为了检测芯片裂纹，电阻器R01设置在要检测芯片裂纹的区域的外周。如果芯片破裂并且电阻器R01的电阻值改变，则检测电阻变化，从而控制诸如上电复位信号的内部信号，并停止电路装置的整个操作，以防止电路故障。因此，系统安全性也可以提高。

9. 发明授权

US06321067B1 Power transmission system IC card and information communication system using IC card 失效
标题翻译：电力传输系统IC卡和使用IC卡的信息通信系统
公开(公告)号：US06321067B1
公开(公告)日：2001-11-20
申请号：US08929060
申请日：1997-09-15
申请人： Takashi Suga , Yoshihiko Hayashi , Ryouzou Yoshino , Kenji Nagai
发明人： Takashi Suga , Yoshihiko Hayashi , Ryouzou Yoshino , Kenji Nagai
IPC分类号： H04B500
CPC分类号： G06K19/0726 , G06K7/0008 , G06K19/0701 , G06K19/0715 , G06K19/0723 , G07C9/00111 , H01Q1/22 , H01Q1/2225 , H01Q7/005 , H02J17/00 , H02J50/12 , H02J50/90
摘要： The present invention comprises a power transmission system, an IC card, and an information communication system using an IC card. In the power transmission system, power is transmitted by radio from the power transmission device to the IC card. In the IC card, the transmitted induced power is converted into a DC voltage, the transmitted induced power or a voltage corresponding to the induced power is detected, and a desired DC voltage to be suppled to the internal circuit is obtained in controlling resistance the detected induced power or the voltage corresponding to the induced power.
摘要翻译：本发明包括电力传输系统，IC卡和使用IC卡的信息通信系统。在电力传输系统中，通过无线电从电力传输装置向IC卡发送电力。在IC卡中，所传输的感应功率被转换为直流电压，检测所传输的感应功率或与感应功率相对应的电压，并且在控制检测到的电阻时获得要提供给内部电路的期望直流电压感应功率或对应于感应功率的电压。

10. 发明授权

US09046417B2 Temperature measuring system, substrate processing apparatus and temperature measuring method 有权
标题翻译：温度测量系统，基板加工设备和温度测量方法
公开(公告)号：US09046417B2
公开(公告)日：2015-06-02
申请号：US13529391
申请日：2012-06-21
申请人： Tatsuo Matsudo , Kenji Nagai
发明人： Tatsuo Matsudo , Kenji Nagai
IPC分类号： G01J3/45 , G01J5/08 , G01J5/00
CPC分类号： G01J5/0896 , G01J5/0007
摘要： The temperature measuring system using optical interference includes a light source which generates measuring light; a spectroscope which measures an interference intensity distribution that is an intensity distribution of reflected light; optical transfer mechanisms which emit light reflected from a surface and a rear surface of the object to be measured to the spectroscope; an optical path length calculation unit which calculates an optical path length by performing Fourier transformation; and a temperature calculation unit which calculates a temperature of the object to be measured on the basis of a relation between optical path lengths and temperatures. The light source has a half-width at half-maximum of a light source spectrum that satisfies conditions based on a wavelength span of the spectroscope. The spectroscope measures the intensity distribution by using the number of samplings that satisfies conditions based on the wavelength span and a maximum measurable thickness.
摘要翻译：使用光学干涉的温度测量系统包括产生测量光的光源; 测量作为反射光的强度分布的干涉强度分布的分光镜; 将从测量对象的表面和后表面反射的光发射到分光器的光学传递机构; 光路长度计算单元，其通过执行傅立叶变换来计算光程长度; 以及温度计算单元，其基于光程长度和温度之间的关系来计算被测量物体的温度。光源具有满足基于分光器的波长跨度的条件的光源光谱的半值的半宽度。分光镜通过使用满足基于波长跨度和最大可测量厚度的条件的采样数来测量强度分布。

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