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1. 发明授权

US08592890B2 Semiconductor memory device and method for manufacturing same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08592890B2
公开(公告)日：2013-11-26
申请号：US13004229
申请日：2011-01-11
申请人： Nobutaka Watanabe , Kazuyuki Higashi , Gaku Sudo
发明人： Nobutaka Watanabe , Kazuyuki Higashi , Gaku Sudo
IPC分类号： H01L29/792 , H01L29/76
CPC分类号： H01L27/11578 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.
摘要翻译：根据一个实施例，半导体存储器件包括层叠体，接触部，半导体部件，电荷存储层和穿透部件。层叠体包括与绝缘膜交替堆叠的电极膜。层叠体的端部的结构是具有设置在每个电极膜上的台阶的台阶构造。触点从端部的上方连接到电极膜。半导体构件设置在除了端部之外的层叠体的一部分中，以在层叠方向上刺穿层叠体。电荷存储层设置在电极膜和半导体部件之间。穿透构件在层叠方向上刺穿端部。穿透构件不包含与电荷存储层相同的材料。

2. 发明申请

US20120061743A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120061743A1
公开(公告)日：2012-03-15
申请号：US13004229
申请日：2011-01-11
申请人： Nobutaka WATANABE , Kazuyuki Higashi , Gaku Sudo
发明人： Nobutaka WATANABE , Kazuyuki Higashi , Gaku Sudo
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11575 , H01L27/11582
摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.
摘要翻译：根据一个实施例，半导体存储器件包括层叠体，接触部，半导体部件，电荷存储层和穿透部件。层叠体包括与绝缘膜交替堆叠的电极膜。层叠体的端部的结构是具有设置在每个电极膜上的台阶的台阶构造。触点从端部的上方连接到电极膜。半导体构件设置在除了端部之外的层叠体的一部分中，以在层叠方向上刺穿层叠体。电荷存储层设置在电极膜和半导体部件之间。穿透构件在层叠方向上刺穿端部。穿透构件不包含与电荷存储层相同的材料。

3. 发明授权

US08866206B2 Integrated circuit device and method for manufacturing same 有权
标题翻译：集成电路装置及其制造方法
公开(公告)号：US08866206B2
公开(公告)日：2014-10-21
申请号：US13409407
申请日：2012-03-01
申请人： Gaku Sudo
发明人： Gaku Sudo
IPC分类号： H01L21/02 , H01L27/088 , H01L21/762 , H01L21/8234
CPC分类号： H01L27/0207 , H01L21/02334 , H01L21/28229 , H01L21/762 , H01L21/76224 , H01L21/76232 , H01L21/823431 , H01L27/0886 , H01L27/1211 , H01L27/228 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： An integrated circuit device includes a plurality of fins on an upper surface of a semiconductor substrate and extending in a first direction, a device isolation insulating film placed between the fins, a gate electrode extending in a second direction crossing the first direction on the insulating film; and an insulating film insulating the fin from the gate electrode. In a first region where a plurality of the fins are consecutively arranged, an upper surface of the device isolation insulating film is located at a first position below an upper end of the fin. In a second region located in the second direction as viewed from the first region, the upper surface of the device isolation insulating film is located at a second position above the upper end of the fin. In the second region, the device isolation insulating film covers entirely a side surface of the fin.
摘要翻译：集成电路装置包括在半导体衬底的上表面上并沿第一方向延伸的多个散热片，设置在散热片之间的器件隔离绝缘膜，在绝缘膜上与第一方向交叉的第二方向延伸的栅电极 ; 以及使所述翅片与所述栅电极绝缘的绝缘膜。在多个翅片连续排列的第一区域中，器件隔离绝缘膜的上表面位于翅片上端下方的第一位置。在从第一区域观察位于第二方向的第二区域中，器件隔离绝缘膜的上表面位于鳍的上端上方的第二位置。在第二区域中，器件隔离绝缘膜完全覆盖翅片的侧表面。

4. 发明授权

US08659159B2 Integrated circuit device with interconnects arranged parallel to each other and connected to contact via, and method for manufacturing same 有权
标题翻译：具有彼此并联并连接到接触通孔的互连的集成电路器件及其制造方法
公开(公告)号：US08659159B2
公开(公告)日：2014-02-25
申请号：US13237825
申请日：2011-09-20
申请人： Gaku Sudo
发明人： Gaku Sudo
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76897 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L23/481 , H01L23/528 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, an integrated circuit device includes a plurality of interconnects and a contact via. The plurality of interconnects are arranged parallel to each other. The contact via is connected to the each of the interconnects. A protrusion is formed at a portion of each of the interconnects connected to the contact via to protrude in a direction of the arrangement. A recess is formed at a portion of the each of the interconnects separated from the portion having the protrusion to recede in the direction. The protrusion formed on one interconnect of two mutually-adjacent interconnects among the plurality of interconnects is opposed to the recess formed in one other interconnect of the two mutually-adjacent interconnects. The portion having the recess is separated from portions on two sides thereof and is separated also from the portion having the protrusion.
摘要翻译：根据一个实施例，集成电路器件包括多个互连和接触通孔。多个互连件彼此平行地布置。接触通孔连接到每个互连。在连接到接触通孔的每个互连件的一部分处形成突起，以沿该布置的方向突出。在与具有突起的部分分离的每个互连部分的一部分上形成凹部，以在该方向上后退。形成在多个互连件中的两个相互相邻的互连件的一个互连上的突起与形成在两个相互相邻的互连的另一个互连中的凹部相对。具有凹部的部分与其两侧的部分分离，并且与具有突出部的部分分离。

5. 发明申请

US20090206414A1 Contact Configuration and Method in Dual-Stress Liner Semiconductor Device 失效
标题翻译：双重应力衬板半导体器件的接触配置与方法
公开(公告)号：US20090206414A1
公开(公告)日：2009-08-20
申请号：US12031272
申请日：2008-02-14
申请人： Gaku Sudo
发明人： Gaku Sudo
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L21/823807 , H01L21/76802 , H01L21/76829 , H01L21/823871 , H01L29/7843
摘要： A method for manufacturing a semiconductor device may comprise forming a conductive layer on a substrate, removing at least one portion of the conductive layer to form a plurality of separate conductive lines, forming a first stress-inducing layer of a first stress type on the conductive lines and the substrate, and removing a portion of the first stress-inducing layer such that a remaining portion of the first stress-inducing layer is disposed on a first subset of the conductive lines but not a second subset of the conductive lines and has a boundary disposed between two of the conductive lines. This method, along with other methods and various semiconductor devices, are described.
摘要翻译：制造半导体器件的方法可以包括在衬底上形成导电层，去除导电层的至少一部分以形成多个单独的导电线，在导电上形成第一应力类型的第一应力诱导层线和衬底，以及去除第一应力诱导层的一部分，使得第一应力诱导层的剩余部分设置在导电线的第一子集上，而不是导电线的第二子集，并且具有边界设置在两条导线之间。描述了该方法以及其他方法和各种半导体器件。

6. 发明申请

US20070034963A1 Semiconductor device with close stress liner film and method of manufacturing the same 失效
标题翻译：具有紧密应力衬膜的半导体器件及其制造方法
公开(公告)号：US20070034963A1
公开(公告)日：2007-02-15
申请号：US11200168
申请日：2005-08-10
申请人： Gaku Sudo
发明人： Gaku Sudo
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/6653 , H01L29/7843
摘要： Aspects of the present disclosure are generally directed to FETs with stress liners that are closer than typical stressed FETs, as well as methods for manufacturing the same. FETE channel sidewall spacers may be removed, or substantially reduced in width, prior to forming the stress liners. This may be performed without destroying the underlying thin oxide layer. The sidewall spacers may be removed substantially reduced either prior to or after silicide formation. Where the sidewall spacers are removed prior to silicide formation, a relatively thin oxide layer on opposing sides of the channel may be used as a mask when forming the silicide. In addition, devices having both an NFET with a closer-than-typical tensile liner and a PFET with a closer-than-typical compressive liner, as well as methods for manufacturing the same, are disclosed.
摘要翻译：本公开的方面通常涉及具有比典型应力FET更接近的应力衬垫的FET以及其制造方法。在形成应力衬垫之前，可以将FETE通道侧壁间隔物移除或宽度大致减小。这可以在不破坏下面的薄氧化物层的情况下进行。在硅化物形成之前或之后，侧壁间隔物可以被除去。在硅化物形成之前去除侧壁间隔物的情况下，在形成硅化物时可以在通道的相对侧上的相对薄的氧化物层用作掩模。此外，公开了具有近似典型的拉伸衬里的NFET和具有比典型的压缩衬垫更近的PFET的器件以及其制造方法。

7. 发明授权

US08785325B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08785325B2
公开(公告)日：2014-07-22
申请号：US13233379
申请日：2011-09-15
申请人： Gaku Sudo
发明人： Gaku Sudo
IPC分类号： H01L21/469 , H01L21/311 , H01L21/32
CPC分类号： H01L21/0338 , H01L21/0337 , H01L27/11526 , H01L27/11548 , H01L43/12 , H01L45/1675
摘要： According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.
摘要翻译：根据一个实施例，一种制造半导体器件的方法，所述方法包括在处理材料上形成第一和第二芯，形成具有堆叠层的覆盖材料包括第一和第二层，覆盖材料覆盖上表面和侧面在第一芯和第二芯的表面上移除覆盖第一芯的第二层，形成在第一芯的侧表面上具有第一层的第一侧壁掩模和在第一芯的侧表面上具有第一和第二层的第二侧壁掩模第二芯通过蚀刻覆盖材料，去除第一和第二芯，并且在使用第一和第二侧壁掩模的条件下通过蚀刻处理的材料来形成具有不同宽度的第一和第二图案。

8. 发明授权

US07867893B2 Method of forming an SOI substrate contact 有权
标题翻译：形成SOI衬底接触的方法
公开(公告)号：US07867893B2
公开(公告)日：2011-01-11
申请号：US11769914
申请日：2007-06-28
申请人： Haining S. Yang , Ramachandra Divakaruni , Byeong Y. Kim , Junedong Lee , Gaku Sudo
发明人： Haining S. Yang , Ramachandra Divakaruni , Byeong Y. Kim , Junedong Lee , Gaku Sudo
IPC分类号： H01L27/01
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/76254 , H01L21/823807 , H01L21/823871 , H01L21/84 , H01L29/7843
摘要： A method is provided of forming a conductive via for contacting a bulk semiconductor region of a semiconductor-on-insulator (“SOI”) substrate. A first opening is formed in a conformal layer overlying a trench isolation region, where the trench isolation region shares an edge with the SOI layer. A dielectric layer then is deposited atop the conformal layer and the trench isolation region, after which a second opening is formed which is aligned with the first opening, the second opening extending through the dielectric layer to expose the bulk semiconductor region. Finally, the conductive via is formed in the second opening.
摘要翻译：提供了形成用于接触绝缘体上半导体（“SOI”）衬底的体半导体区域的导电通孔的方法。第一开口形成在覆盖沟槽隔离区域的共形层中，其中沟槽隔离区域与SOI层共享边缘。然后在保形层和沟槽隔离区的顶部沉积电介质层，然后形成与第一开口对准的第二开口，第二开口延伸穿过电介质层以暴露体半导体区域。最后，在第二开口中形成导电通孔。

9. 发明申请

US20090032843A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090032843A1
公开(公告)日：2009-02-05
申请号：US12179384
申请日：2008-07-24
申请人： Atsushi OHTA , Gaku Sudo
发明人： Atsushi OHTA , Gaku Sudo
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/28052 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/66628 , H01L29/66636
摘要： A semiconductor device includes a semiconductor substrate, and a MIS type FET provided on the semiconductor substrate, the MIS type FET includes a gate insulating film provide on the semiconductor substrate, a gate electrode provided on the gate insulating film, a channel region provided in the semiconductor substrate and being isolated from the gate electrode by the gate insulating film, source/drain layers sandwiching the channel region, the source/drain layers including semiconductor layers having lattice spacing which is different from that of the semiconductor substrate and having uniform height, and a metal silicide layer provided on a region including a top surfaces of the source/drain layers and failing to provide on the channel region.
摘要翻译：半导体器件包括半导体衬底和设置在半导体衬底上的MIS型FET，MIS型FET包括在半导体衬底上提供的栅极绝缘膜，设置在栅极绝缘膜上的栅电极，设置在栅极绝缘膜上的沟道区半导体衬底，并且通过栅极绝缘膜与栅电极隔离，夹着沟道区的源极/漏极层，源极/漏极层包括具有与半导体衬底不同的晶格间距并具有均匀高度的半导体层，以及金属硅化物层，设置在包括源极/漏极层的顶表面的区域上，并且不能在沟道区域上提供。

10. 发明申请

US20070246741A1 Stress relaxation for top of transistor gate 失效
标题翻译：晶体管栅极顶部的应力松弛
公开(公告)号：US20070246741A1
公开(公告)日：2007-10-25
申请号：US11409090
申请日：2006-04-24
申请人： Gaku Sudo
发明人： Gaku Sudo
IPC分类号： H01L29/73
CPC分类号： H01L21/31155 , H01L29/7843
摘要： An improved way to apply tensile or compressive stress to one or more transistors on a semiconductor device is described. A portion of the tensile or compressive stress liner may be removed or modified such that a reduced amount of stress, or even no stress, is applied above the transistor gate. This may cause edges of the stress liner to be adjacent to and on either side of the channel, thus, increasing the stress effect. To produce this stress liner structure, the stress liner may be applied and then a portion of the stress liner is modified to reduce the stress in that portion, such as through ion implantation. The stress liner portion may be modified to have a reduced stress by, for example, implanting certain ions such as germanium or xenon ions therein.
摘要翻译：描述了对半导体器件上的一个或多个晶体管施加拉伸或压缩应力的改进方法。可以去除或修改拉伸或压缩应力衬垫的一部分，使得在晶体管栅极上方施加减小的应力量，甚至没有应力。这可能导致应力衬垫的边缘与通道的任一侧相邻并且在通道的任一侧上，因此增加了应力效应。为了产生这种应力衬垫结构，可以施加应力衬垫，然后改变一部分应力衬垫以减小该部分中的应力，例如通过离子注入。可以通过例如在其中注入某些离子如锗或氙离子来将应力衬垫部分修改为具有减小的应力。

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