专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050275658A1 Information processing apparatus with a cache memory and information processing method 有权
标题翻译：具有高速缓冲存储器和信息处理方法的信息处理装置
公开(公告)号：US20050275658A1
公开(公告)日：2005-12-15
申请号：US11141700
申请日：2005-05-31
申请人： Nobuo Sasaki , Takeshi Yamazaki , Atsushi Kunimatsu , Hideki Yasukawa
发明人： Nobuo Sasaki , Takeshi Yamazaki , Atsushi Kunimatsu , Hideki Yasukawa
IPC分类号： G06F12/08 , G06F12/00 , G09G5/36
CPC分类号： G06F12/0844 , G06F12/0862 , G06F12/0864 , G06F2212/6024
摘要： A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.
摘要翻译：二次纹理缓存由多个纹理单元通常使用，并将纹理数据的一部分存储在主存储器中。高速缓存控制CPU根据多个纹理单元的高速缓存未命中来控制从主存储器到次纹理高速缓存的再填充操作，以便抑制二次纹理高速缓存中的抖动的发生。当多个操作单元以预定的时间差访问相同的存储器地址时，高速缓存控制CPU抑制再填充操作的发生。

2. 发明授权

US07644234B2 Information processing apparatus with a cache memory and information processing method 有权
标题翻译：具有高速缓冲存储器和信息处理方法的信息处理装置
公开(公告)号：US07644234B2
公开(公告)日：2010-01-05
申请号：US11141700
申请日：2005-05-31
申请人： Nobuo Sasaki , Takeshi Yamazaki , Atsushi Kunimatsu , Hideki Yasukawa
发明人： Nobuo Sasaki , Takeshi Yamazaki , Atsushi Kunimatsu , Hideki Yasukawa
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0844 , G06F12/0862 , G06F12/0864 , G06F2212/6024
摘要： A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.
摘要翻译：二次纹理缓存由多个纹理单元通常使用，并将纹理数据的一部分存储在主存储器中。高速缓存控制CPU根据多个纹理单元的高速缓存未命中来控制从主存储器到次纹理高速缓存的再填充操作，以便抑制二次纹理高速缓存中的抖动的发生。当多个操作单元以预定的时间差访问相同的存储器地址时，高速缓存控制CPU抑制再填充操作的发生。

3. 发明授权

US06809734B2 Resource dedication system and method for a computer architecture for broadband networks 有权
标题翻译：宽带网络计算机架构的资源投入系统和方法
公开(公告)号：US06809734B2
公开(公告)日：2004-10-26
申请号：US09815558
申请日：2001-03-22
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Charles Ray Johns , Shigehiro Asano , Atsushi Kunimatsu , Yukio Watanabe
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Charles Ray Johns , Shigehiro Asano , Atsushi Kunimatsu , Yukio Watanabe
IPC分类号： G06T120
CPC分类号： G06F9/4893 , A63F2300/20 , A63F2300/538 , Y02D10/24
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

4. 发明授权

US07233998B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07233998B2
公开(公告)日：2007-06-19
申请号：US09816004
申请日：2001-03-22
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

5. 发明授权

US07720982B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07720982B2
公开(公告)日：2010-05-18
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

6. 发明申请

US20070168538A1 Computer architecture and software cells for broadband networks 有权
公开(公告)号：US20070168538A1
公开(公告)日：2007-07-19
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Hofstee , Martin Hopkins , Charles Johns , James Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Hofstee , Martin Hopkins , Charles Johns , James Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

7. 发明授权

US06919896B2 System and method of optimizing graphics processing 有权
标题翻译：优化图形处理的系统和方法
公开(公告)号：US06919896B2
公开(公告)日：2005-07-19
申请号：US10095213
申请日：2002-03-11
申请人： Nobuo Sasaki , Takeshi Yamazaki
发明人： Nobuo Sasaki , Takeshi Yamazaki
IPC分类号： G06T11/00 , G06F9/50 , G06T1/20 , G06T15/00 , G09G5/393 , G06F15/80
CPC分类号： G06F9/5083 , G06F9/5066 , G06F2209/501 , G06T1/20 , G06T15/005 , G06T2210/52 , G09G5/393 , G09G2360/121
摘要： A method and system for optimizing the processing of graphics is disclosed. The system may comprise at least one geometry processor and at least one graphics processor. A communication channel permits communication between the geometry and graphics processors. A control processor may communicate with the geometry and graphics processor through the communications channel. A method of processing graphics data in a computer system is provided to determine whether the geometry and graphics processors are being efficiently utilized. If necessary, one or more of the geometry and graphics processors are selectively assigned or unassigned to improve the efficiency of the graphics processing circuitry in performing the graphics task.
摘要翻译：公开了一种用于优化图形处理的方法和系统。该系统可以包括至少一个几何处理器和至少一个图形处理器。通信通道允许几何和图形处理器之间的通信。控制处理器可以通过通信信道与几何和图形处理器进行通信。提供了一种在计算机系统中处理图形数据的方法，以确定几何图形处理器是否被有效利用。如果需要，一个或多个几何和图形处理器被选择性地分配或未分配，以提高图形处理电路在执行图形任务时的效率。

8. 发明授权

US08996440B2 Information processing apparatus, information processing method, and program 有权
标题翻译：信息处理装置，信息处理方法和程序
公开(公告)号：US08996440B2
公开(公告)日：2015-03-31
申请号：US13474159
申请日：2012-05-17
申请人： Takeshi Yamazaki , Seiji Wada , Yoshihiro Wakita , Koji Kashima , Natsuki Kimura
发明人： Takeshi Yamazaki , Seiji Wada , Yoshihiro Wakita , Koji Kashima , Natsuki Kimura
IPC分类号： G06N5/02 , G06Q10/10
CPC分类号： G06Q10/109
摘要： An information processing apparatus configured to create a schedule to be presented to a user includes an estimation unit and a creation unit. The estimation unit is configured to estimate whether or not the user acts in accordance with a first schedule including a task to do for accomplishing a preset aim. The creation unit is configured to create, when estimated that the user does not act in accordance with the first schedule, a new second schedule for accomplishing the aim from a state of the user who acts without following the first schedule.
摘要翻译：被配置为创建要呈现给用户的日程表的信息处理设备包括估计单元和创建单元。估计单元被配置为估计用户是否根据包括要完成预设目标的任务的第一调度进行动作。创建单元被配置为当估计用户不按照第一时间表行动时创建新的第二计划，用于从不遵循第一进度的行为的用户的状态完成目标。

9. 发明授权

US08774895B2 Electroencephalographic headset 有权
标题翻译：脑电耳机
公开(公告)号：US08774895B2
公开(公告)日：2014-07-08
申请号：US13616185
申请日：2012-09-14
申请人： Seiji Wada , Takeshi Yamazaki , Natsuki Kimura , Yoshihiro Wakita , Koji Kashima , Tomiji Tanaka , Mitsuhiro Nakamura , Tatsumi Sakaguchi , Haruhiko Soma , Takuro Yamamoto
发明人： Seiji Wada , Takeshi Yamazaki , Natsuki Kimura , Yoshihiro Wakita , Koji Kashima , Tomiji Tanaka , Mitsuhiro Nakamura , Tatsumi Sakaguchi , Haruhiko Soma , Takuro Yamamoto
IPC分类号： A61B5/0478 , A61B5/00
CPC分类号： A61B5/0478 , A61B5/6803 , A61B5/6814 , A61B5/6843
摘要： An electroencephalographic headset includes: a supporter that includes expanding and contracting wires each having expansion and contraction properties and is to be attached to a head of a user by expansion and contraction of each of the expanding and contracting wires; and a plurality of electrodes that are provided to the supporter in defined placement.
摘要翻译：脑电耳机包括：支撑件，其包括每个具有伸缩性能的伸缩线，并且通过每个伸缩线的伸缩来附接到使用者的头部; 以及以规定的位置设置在支撑体上的多个电极。

10. 发明授权

US08761554B2 Wavelength selective switch 有权
标题翻译：波长选择开关
公开(公告)号：US08761554B2
公开(公告)日：2014-06-24
申请号：US13419646
申请日：2012-03-14
申请人： Koji Matsumoto , Satoshi Watanabe , Toshiro Okamura , Takeshi Yamazaki
发明人： Koji Matsumoto , Satoshi Watanabe , Toshiro Okamura , Takeshi Yamazaki
IPC分类号： G02B6/26 , G02B6/42
CPC分类号： G02B6/3518 , G02B6/3534
摘要： Provided is a wavelength selective switch, which includes: an input/output unit; a dispersive portion; a condensing optical system; and the deflection portion. The input/output unit has input/output ports. The dispersive portion disperses signal light incident from the input/output ports. The condensing optical system condenses a plurality of signal light beams dispersed by the dispersive portion. The deflection portion has a plurality of deflection elements. The deflection elements deflect, along a second direction, the signal light beams condensed by the condensing optical system. In the condensing optical system, the aberration amount of the meridional component in a sagittal coma aberration remains substantially constant irrespective of an angle formed between the optical axis of the condensing optical system and a signal light beam incident on the condensing optical system from the input/output portion, at an incident position of the incident signal light beam at a certain height in the second direction.
摘要翻译：提供一种波长选择开关，其包括：输入/输出单元; 分散部分; 聚光光学系统; 和偏转部。输入/输出单元具有输入/输出端口。色散部分分散从输入/输出端口入射的信号光。聚光光学系统凝聚由分散部分散射的多个信号光束。偏转部分具有多个偏转元件。偏转元件沿着第二方向偏转由聚光光学系统会聚的信号光束。在聚光光学系统中，与聚光光学系统的光轴和入射到聚光光学系统的信号光束之间的角度不同，矢状彗差中的子午分量的像差量保持基本恒定，在入射信号光束的入射位置处，在第二方向上处于一定高度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式