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1. 发明申请

US20060190851A1 Asynchronous circuit design tool and computer program product 有权
标题翻译：异步电路设计工具和计算机程序产品
公开(公告)号：US20060190851A1
公开(公告)日：2006-08-24
申请号：US11037139
申请日：2005-01-19
申请人： Nobuo Karaki , Tak Lee
发明人： Nobuo Karaki , Tak Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5059
摘要： It is the object of the present invention to provide asynchronous circuit design tools for those engineers who are versed in standard hardware description languages (HDLs), which is widely used in industry mainly for synchronous circuit design, to design asynchronous circuits with relative ease. To accomplish the object, the asynchronous circuit design tools of the present invention include a translator for transforming a code written in an asynchronous circuit design language, which is based on a standard HDL and includes minimal primitives for describing the communications between asynchronous circuit blocks or processes, into a code written in a standard HDL, which is originally developed for synchronous circuit design. The codes transformed into the standard HDL can be functionally verified by using commercially available simulators, which are originally developed for verifying synchronous circuit design.
摘要翻译：本发明的目的是为那些在业界主要用于同步电路设计中广泛使用的标准硬件描述语言（HDL）的工程师提供异步电路设计工具，相对容易地设计异步电路。为了实现该目的，本发明的异步电路设计工具包括用于变换以异步电路设计语言编写的代码的翻译器，其基于标准HDL并且包括用于描述异步电路块或处理之间的通信的最小原语，转换为标准HDL编写的代码，最初用于同步电路设计。转换为标准HDL的代码可以通过使用商业上可用的模拟器进行功能验证，这些模拟器最初用于验证同步电路设计。

2. 发明授权

US08058982B2 Information display systems and methods for hybrid vehicles 有权
标题翻译：混合动力汽车的信息显示系统和方法
公开(公告)号：US08058982B2
公开(公告)日：2011-11-15
申请号：US12202162
申请日：2008-08-29
申请人： Paul S. Crowe , Myra Ma , Shawn Brewer , John W. Espinosa , Tak Lee , Derek S. Sancer
发明人： Paul S. Crowe , Myra Ma , Shawn Brewer , John W. Espinosa , Tak Lee , Derek S. Sancer
IPC分类号： B60Q1/00 , G09F9/00 , G05D3/00 , G06F7/00 , G06G7/70
CPC分类号： B60W20/00 , B60K6/48 , B60K35/00 , B60L2240/421 , B60L2240/423 , B60L2240/441 , B60L2240/486 , B60L2250/16 , B60W10/06 , B60W10/08 , B60W2050/048 , B60W2510/0604 , B60W2510/0638 , B60W2510/081 , B60W2510/1015 , B60W2510/104 , B60W2510/244 , B60W2540/06 , B60W2540/10 , B60W2540/12 , B60W2710/0666 , B60W2710/083 , B60Y2200/90 , Y02T10/6221 , Y02T10/6286 , Y02T10/642 , Y02T10/84
摘要： Information display systems capable of iconically representing the components of a hybrid powertrain and method thereof. In operation, the information display systems indicate the specific powertrain components in the hybrid system that are active in various hybrid operational modes (e.g., electric launch, blended torque, etc.). In particular, active components are highlighted (i.e., increased intensity) by the display and non-active components are faded (i.e., decreased intensity). In one embodiment, the vehicle wheels are depicted with a static intensity in-between that of the active components and the non-active components. This allows the vehicle operator to clearly see which components are active during each hybrid system mode, and to gain a simplified picture of hybrid system behavior during normal operation at a glance.
摘要翻译：能够以图形方式表示混合动力总成的部件的信息显示系统及其方法。在操作中，信息显示系统指示混合系统中在各种混合操作模式（例如，电动发射，混合扭矩等）中有效的特定动力系分量。特别地，有源组件被显示器突出显示（即，增强的强度），而非有源组件被褪色（即强度降低）。在一个实施例中，车轮被描绘成具有在活动部件和非活动部件之间的静态强度。这允许车辆操作者在每个混合系统模式期间清楚地看到哪些部件是活动的，并且在正常操作期间一目了然地获得混合系统行为的简化图。

3. 外观设计

USD647832S1 Truck hood 有权
标题翻译：卡车罩
公开(公告)号：USD647832S1
公开(公告)日：2011-11-01
申请号：US29388490
申请日：2011-03-29
申请人： Dimitri T. Medina , Tak Lee , Scott M. Conway , Derek Sancer , Chris I. Ito , Aaron M. Elliott , Bryan W. Delashaw
设计人： Dimitri T. Medina , Tak Lee , Scott M. Conway , Derek Sancer , Chris I. Ito , Aaron M. Elliott , Bryan W. Delashaw

4. 发明申请

US20070162814A1 LDPC (low density parity check) code size adjustment by shortening and puncturing 失效
标题翻译：通过缩短和穿孔对LDPC（低密度奇偶校验）码大小进行调整
公开(公告)号：US20070162814A1
公开(公告)日：2007-07-12
申请号：US11417316
申请日：2006-05-03
申请人： Ba-Zhong Shen , Tak Lee , Kelly Cameron
发明人： Ba-Zhong Shen , Tak Lee , Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1185 , H03M13/1188 , H03M13/618 , H03M13/6362
摘要： LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.
摘要翻译： LDPC（低密度奇偶校验）码字大小调整通过缩短和删截。可以使用选择的缩短和删截从初始LDPC码生成各种LDPC编码信号。使用LDPC码大小调整方法，硬件设计能够处理原始LDPC码的单个通信设备也能够在进行适当的缩短和删截之后处理由原始LDPC码构成的各种其他LDPC码。这提供了重要的设计简化和复杂性的降低，因为可以实现相同的硬件以适应从原始LDPC码产生的各种LDPC码。因此，可以实现能够处理几个所生成的LDPC码的具有多LDPC码的通信装置。这种方法允许在LDPC码设计中具有极大的灵活性，因为可以在执行缩短和删截之后维持原始码率。

5. 发明申请

US20100052888A1 INFORMATION DISPLAY SYSTEMS AND METHODS FOR HYBRID VEHICLES 有权
标题翻译：信息显示系统和混合动力车辆的方法
公开(公告)号：US20100052888A1
公开(公告)日：2010-03-04
申请号：US12202162
申请日：2008-08-29
申请人： Paul S. Crowe , Myra Ma , Shawn Brewer , John W. Espinosa , Tak Lee , Derek S. Sancer
发明人： Paul S. Crowe , Myra Ma , Shawn Brewer , John W. Espinosa , Tak Lee , Derek S. Sancer
IPC分类号： B60Q1/00
CPC分类号： B60W20/00 , B60K6/48 , B60K35/00 , B60L2240/421 , B60L2240/423 , B60L2240/441 , B60L2240/486 , B60L2250/16 , B60W10/06 , B60W10/08 , B60W2050/048 , B60W2510/0604 , B60W2510/0638 , B60W2510/081 , B60W2510/1015 , B60W2510/104 , B60W2510/244 , B60W2540/06 , B60W2540/10 , B60W2540/12 , B60W2710/0666 , B60W2710/083 , B60Y2200/90 , Y02T10/6221 , Y02T10/6286 , Y02T10/642 , Y02T10/84
摘要： Information display systems capable of iconically representing the components of a hybrid powertrain and method thereof. In operation, the information display systems indicate the specific powertrain components in the hybrid system that are active in various hybrid operational modes (e.g., electric launch, blended torque, etc.). In particular, active components are highlighted (i.e., increased intensity) by the display and non-active components are faded (i.e., decreased intensity). In one embodiment, the vehicle wheels are depicted with a static intensity in-between that of the active components and the non-active components. This allows the vehicle operator to clearly see which components are active during each hybrid system mode, and to gain a simplified picture of hybrid system behavior during normal operation at a glance.
摘要翻译：能够以图形方式表示混合动力总成的部件的信息显示系统及其方法。在操作中，信息显示系统指示混合系统中在各种混合操作模式（例如，电动发射，混合扭矩等）中有效的特定动力系分量。特别地，有源组件被显示器突出显示（即，增强的强度），而非有源组件被褪色（即强度降低）。在一个实施例中，车轮被描绘成具有在活动部件和非活动部件之间的静态强度。这允许车辆操作者在每个混合系统模式期间清楚地看到哪些部件是活动的，并且在正常操作期间一目了然地获得混合系统行为的简化图。

6. 发明申请

US20070291891A1 System and method for adjusting the phase of a frequency-locked clock 有权
标题翻译：用于调节锁频时钟相位的系统和方法
公开(公告)号：US20070291891A1
公开(公告)日：2007-12-20
申请号：US11892607
申请日：2007-08-24
申请人： Tak Lee , Jeffrey Putnam , James Cavallo
发明人： Tak Lee , Jeffrey Putnam , James Cavallo
IPC分类号： H03D3/24
CPC分类号： H03L7/00 , H04J3/0682
摘要： A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the system to ensure that underflow or overflow of the numerically controlled oscillator is prevented. In another embodiment, additional components are included to ensure that output pulses from the numerically controlled oscillator do not occur within a minimum time interval. The method includes deriving a phase adjustment factor, adding the phase adjustment factor to a frequency control word, providing the modified frequency control word to a numerically controlled oscillator and generating a phase shifted, frequency-locked output signal.
摘要翻译：提供了一种用于调节锁频时钟信号的相位的时钟信号再生系统和方法。该系统包括数控振荡器，时钟源和加法器。在一个实施例中，系统中包括附加组件以确保防止数控振荡器的下溢或溢出。在另一个实施例中，包括附加组件以确保来自数控振荡器的输出脉冲不会在最小时间间隔内发生。该方法包括导出相位调整因子，将相位调整因子加到频率控制字上，将经修改的频率控制字提供给数控振荡器并产生相移的频率锁定输出信号。

7. 发明申请

US20070157062A1 Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices 失效
标题翻译：通过扫描子矩阵实现LDPC（低密度奇偶校验）解码器
公开(公告)号：US20070157062A1
公开(公告)日：2007-07-05
申请号：US11360268
申请日：2006-02-23
申请人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
发明人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/255 , H03M13/27 , H03M13/6362 , H03M13/6566
摘要： Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).
摘要翻译：通过扫描子矩阵实现LDPC（低密度奇偶校验）解码器。提出了一种解码处理与LDPC码对应的低密度奇偶校验矩阵的各个子矩阵的列和行的LDPC编码信号的新方法。低密度奇偶校验矩阵可以根据它的每个子矩阵划分成行和列，并且这些子矩阵中的每一个也包括相应的行和列。例如，当执行位节点处理时，可以一起处理1个或更多个子矩阵的相同列（例如，1个或更多个子矩阵中的所有1个SUP列，全部2个SUP 1个或更多个子矩阵中的 / nd>列等）。类似地，当执行校验节点处理时，可以一起处理1个或更多个子矩阵的相同行（例如，1个或更多个子矩阵中的所有1 ^{行，全部2个 1个或多个子矩阵中的行等）。}

8. 发明申请

US20070157061A1 Sub-matrix-based implementation of LDPC (Low Density Parity Check ) decoder 失效
标题翻译： LDPC（低密度奇偶校验）解码器的基于子矩阵的实现
公开(公告)号：US20070157061A1
公开(公告)日：2007-07-05
申请号：US11360267
申请日：2006-02-23
申请人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
发明人： Tak Lee , Hau Tran , Ba-Zhong Shen , Kelly Cameron
IPC分类号： H03M13/00
CPC分类号： H03M13/116 , H03M13/1137 , H03M13/255 , H03M13/27 , H03M13/6362 , H03M13/6566
摘要： Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder. A novel approach is presented by which an LDPC coded signal is decoded by processing 1 sub-matrix at a time. A low density parity check matrix corresponding to the LDPC code includes rows and columns of sub-matrices. For example, when performing bit node processing, 1 or more sub-matrices in a column are processed; when performing check node processing, 1 or more sub-matrices in a row are processed. If desired, when performing bit node processing, the sub-matrices in each column are successively processed together (e.g., all column 1 sub-matrices, all column 2 sub-matrices, etc.). Analogously, when performing check node processing, the sub-matrices in each row can be successively processed together (e.g., all row 1 sub-matrices, all row 2 sub-matrices in row 2, etc.).
摘要翻译： LDPC（低密度奇偶校验）解码器的基于子矩阵的实现。提出了一种新颖的方法，通过该方法通过一次处理1个子矩阵对LDPC编码信号进行解码。对应于LDPC码的低密度奇偶校验矩阵包括子矩阵的行和列。例如，当执行位节点处理时，处理列中的一个或多个子矩阵; 当执行校验节点处理时，处理一行中的一个或多个子矩阵。如果需要，当执行位节点处理时，每列中的子矩阵被连续处理（例如，所有列1个子矩阵，全部2个子矩阵等）。类似地，当执行校验节点处理时，可以一起连续地处理每行中的子矩阵（例如，所有行1子矩阵，行2中的所有行2子矩阵等）。

9. 发明申请

US20060156169A1 LDPC (Low Density Parity Check) coding and interleaving implemented in MIMO communication systems 有权
标题翻译：在MIMO通信系统中实现的LDPC（低密度奇偶校验）编码和交织
公开(公告)号：US20060156169A1
公开(公告)日：2006-07-13
申请号：US11264998
申请日：2005-11-02
申请人： Ba-Zhong Shen , Christopher Hansen , Joseph Lauer , Kelly Cameron , Tak Lee , Hau Tran
发明人： Ba-Zhong Shen , Christopher Hansen , Joseph Lauer , Kelly Cameron , Tak Lee , Hau Tran
IPC分类号： H03M13/00
CPC分类号： H04L27/2626 , H03M13/1148 , H03M13/116 , H03M13/255 , H03M13/6362 , H04B7/0617 , H04L1/0057 , H04L1/0071 , H04L5/0023 , H04L27/2647 , H04L27/34
摘要： LDPC (Low Density Parity Check) coding and interleaving implemented in multiple-input-multiple-output (MIMO) communication systems. Initially, a novel approach is presented by which a wide variety of irregular LDPC codes may be generated using GRS or RS codes. These irregular LDPC codes can provide better overall performance than regular LDPC codes in terms of providing for lower BER (Bit Error Rate) as a function of SNR (Signal to Noise Ratio). A variety of communication device types are also presented that may employ the error correcting coding using a GRS-based irregular LDPC code, along with appropriately selected interleaving, to provide for even better performance. These communication devices may be implemented to in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).
摘要翻译：在多输入多输出（MIMO）通信系统中实现的LDPC（低密度奇偶校验）编码和交织。最初，提出了一种新颖的方法，通过该方法可以使用GRS或RS代码生成各种不规则的LDPC码。在提供作为SNR（信噪比）的函数的较低BER（误码率）方面，这些不规则LDPC码可以提供比常规LDPC码更好的总体性能。还提出了各种通信设备类型，其可以采用基于GRS的不规则LDPC码的纠错编码以及适当选择的交织，以提供更好的性能。这些通信设备可以被实现在无线通信系统中，包括符合由IEEE 802.11n任务组（即，正在努力制定802.11Gn（高吞吐量）的标准的任务组）开发的推荐做法和标准的通信系统，）。

10. 发明申请

US20100023670A1 METHOD AND SYSTEM FOR ROUTING DATA IN A PARALLEL TURBO DECODER 有权
标题翻译：用于在并行涡轮解码器中路由数据的方法和系统
公开(公告)号：US20100023670A1
公开(公告)日：2010-01-28
申请号：US12180205
申请日：2008-07-25
申请人： Tak Lee , Bazhong Shen
发明人： Tak Lee , Bazhong Shen
IPC分类号： G06F13/38
CPC分类号： G06F13/387 , Y02D10/14 , Y02D10/151
摘要： Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power consumption, and/or latency of parallel Turbo decoders. According to certain aspects of the present invention, address routing-networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from the processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency.
摘要翻译：这里描述了用于在并行Turbo解码器中路由数据的系统和方法。本发明的方面解决了减少并行Turbo解码器的物理电路面积，功耗和/或等待时间的需要。根据本发明的某些方面，可以消除地址路由网络，从而减少电路面积和功耗。根据本发明的其他方面，地址生成可以从处理器移动到专用地址生成模块，从而降低连接开销和等待时间。

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