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    • 7. 发明申请
    • GLOW PLUG CONTROL DRIVE METHOD AND GLOW PLUG DRIVE CONTROL SYSTEM
    • GLOW插头控制驱动方法和GLOW PLUG驱动控制系统
    • US20130255615A1
    • 2013-10-03
    • US13993165
    • 2011-12-06
    • Yoshito HujishiroYutaka TanakaTomohiro Nakamura
    • Yoshito HujishiroYutaka TanakaTomohiro Nakamura
    • F02P23/00
    • F02P23/00F02D2041/2027F02P19/02F02P19/022F02P19/023F02P19/026F23Q7/001
    • To suppress current fluctuations upon commencement of driving and prolong lifespan by reducing electric stress caused by current fluctuations.A glow plug 1, a glow switch 2, and a stabilizing coil 3 are series-connected, and upon commencement of the driving of the glow plug 1, a repetition frequency of PWM signals that control the opening and closing of the glow switch 2 is made into a higher frequency than a repetition frequency in a normal drive state and the opening and closing of the glow switch 2 is controlled (S104), and when a predetermined drive shift condition has been met (S106), the repetition frequency of the PWM signals is returned to the frequency during normal driving and the opening and closing of the glow switch 2 is controlled (S108), whereby the current upon commencement of driving is smoothed and the occurrence of an instantaneous large current is suppressed.
    • 为了抑制驱动开始时的电流波动,通过减少由电流波动引起的电应力来延长寿命。 电热塞1,辉光开关2和稳定线圈3是串联的,并且在电热塞1的驱动开始时,控制辉光开关2的打开和关闭的PWM信号的重复频率是 在正常驱动状态下被制成比重复频率高的频率,并且控制辉光开关2的打开和关闭(S104),并且当满足预定的驱动移位条件(S106)时,PWM的重复频率 信号在正常驱动期间返回到频率,并且控制辉光开关2的打开和关闭(S108),从而驱动开始时的电流平滑,并且抑制了瞬时大电流的发生。
    • 8. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08159852B2
    • 2012-04-17
    • US12398839
    • 2009-03-05
    • Toshiyuki KouchiYutaka Tanaka
    • Toshiyuki KouchiYutaka Tanaka
    • G11C5/02
    • G11C8/16G11C11/412
    • A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
    • 半导体存储器件包括第一和第二驱动晶体管; 第一和第二负载晶体管; 以及第一和第二传输晶体管。 它们各自的漏极扩散层彼此隔离。 半导体存储器件还包括其中布置第一和第二驱动晶体管,第一和第二负载晶体管以及第一和第二传输晶体管的位单元; 用于连接第一驱动晶体管,第一负载晶体管和第一透射晶体管的各自的漏极的第一布线; 以及用于连接其第二驱动晶体管,第二负载晶体管和第二传输晶体管的各自的漏极的第二布线。
    • 9. 发明申请
    • SEMICONDUCTOR MEMORY DEVICE
    • 半导体存储器件
    • US20090268499A1
    • 2009-10-29
    • US12398839
    • 2009-03-05
    • Toshiyuki KouchiYutaka Tanaka
    • Toshiyuki KouchiYutaka Tanaka
    • G11C5/02G11C5/06G11C8/16
    • G11C8/16G11C11/412
    • A semiconductor memory device includes first and second driving transistors; first and second load transistors; and first and second transmission transistors. Their respective drain diffusion layers of the transistors are isolated from one another. The semiconductor memory device also includes a bit cell in which the first and second driving transistors, the first and second load transistors, and the first and second transmission transistors are arranged; a first wiring for connecting their respective drains of the first driving transistor, the first load transistor, and the first transmission transistor; and a second wiring for connecting their respective drains of the second driving transistor, the second load transistor, and the second transmission transistor.
    • 半导体存储器件包括第一和第二驱动晶体管; 第一和第二负载晶体管; 以及第一和第二传输晶体管。 它们各自的漏极扩散层彼此隔离。 半导体存储器件还包括其中布置第一和第二驱动晶体管,第一和第二负载晶体管以及第一和第二传输晶体管的位单元; 用于连接第一驱动晶体管,第一负载晶体管和第一透射晶体管的各自的漏极的第一布线; 以及用于连接其第二驱动晶体管,第二负载晶体管和第二传输晶体管的各自的漏极的第二布线。