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1. 发明授权

US08284607B2 Semiconductor memory system including a plurality of semiconductor memory devices 有权
标题翻译：半导体存储器系统包括多个半导体存储器件
公开(公告)号：US08284607B2
公开(公告)日：2012-10-09
申请号：US12645104
申请日：2009-12-22
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
摘要翻译：通信线路连接到第一和第二芯片，并保持在第一信号电平。监视电路将通信线路的信号电平从第一信号改变到第二信号电平，而第一和第二芯片中的一个使用大于参考电流的电流。当通信线路的信号电平为第二信号电平时，第一和第二芯片中的另一个被控制为等待状态，该等待状态不转移到使用大于参考电流的电流的操作状态。

2. 发明授权

US07768830B2 Semiconductor memory device capable of correcting a read level properly 有权
标题翻译：能够正确地校正读取电平的半导体存储器件
公开(公告)号：US07768830B2
公开(公告)日：2010-08-03
申请号：US12416750
申请日：2009-04-01
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3418 , G11C2211/5646 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.
摘要翻译：在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平第一存储器单元，然后读取第一存储器单元的阈值电平。存储部存储校正等级。

3. 发明授权

US07656711B2 Semiconductor memory system including a plurality of semiconductor memory devices 有权
标题翻译：半导体存储器系统包括多个半导体存储器件
公开(公告)号：US07656711B2
公开(公告)日：2010-02-02
申请号：US12027546
申请日：2008-02-07
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
摘要翻译：通信线路连接到第一和第二芯片，并保持在第一信号电平。监视电路将通信线路的信号电平从第一信号改变到第二信号电平，而第一和第二芯片中的一个使用大于参考电流的电流。当通信线路的信号电平为第二信号电平时，第一和第二芯片中的另一个被控制为等待状态，该等待状态不转移到使用大于参考电流的电流的操作状态。

4. 发明授权

US07593267B2 Method of writing data to a semiconductor memory device 有权
标题翻译：将数据写入半导体存储器件的方法
公开(公告)号：US07593267B2
公开(公告)日：2009-09-22
申请号：US11832990
申请日：2007-08-02
申请人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
发明人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/28 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648 , G11C2216/14
摘要： A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.
摘要翻译：一种将数据写入具有存储单元的半导体存储器件的方法，每个存储器单元以非易失性方式存储由其阈值电压定义的数据，该器件具有彼此相邻布置的第一和第二存储器单元，以顺序写入该存储器单元该方法包括：执行用于将由低于期望阈值电压的阈值电压定义的数据写入第一存储单元的第一数据写入操作; 执行用于将数据写入第二存储单元的第二数据写入操作; 以及执行用于将由所述期望阈值电压定义的数据写入所述第一存储单元的第三数据写入操作。

5. 发明申请

US20070280000A1 METHOD OF WRITING DATA TO A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：将数据写入半导体存储器件的方法
公开(公告)号：US20070280000A1
公开(公告)日：2007-12-06
申请号：US11832990
申请日：2007-08-02
申请人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
发明人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/28 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648 , G11C2216/14
摘要： A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.
摘要翻译：一种将数据写入具有存储单元的半导体存储器件的方法，每个存储器单元以非易失性方式存储由其阈值电压定义的数据，该器件具有彼此相邻布置的第一和第二存储器单元，以顺序写入该存储器单元该方法包括：执行用于将由低于期望阈值电压的阈值电压定义的数据写入第一存储单元的第一数据写入操作; 执行用于将数据写入第二存储单元的第二数据写入操作; 以及执行用于将由所述期望阈值电压定义的数据写入所述第一存储单元的第三数据写入操作。

6. 发明授权

US07257032B2 Method of writing data to a semiconductor memory device 有权
标题翻译：将数据写入半导体存储器件的方法
公开(公告)号：US07257032B2
公开(公告)日：2007-08-14
申请号：US11270499
申请日：2005-11-10
申请人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
发明人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/28 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648 , G11C2216/14
摘要： A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.
摘要翻译：一种将数据写入具有存储单元的半导体存储器件的方法，每个存储器单元以非易失性方式存储由其阈值电压定义的数据，该器件具有彼此相邻布置的第一和第二存储器单元，以顺序写入该存储器单元该方法包括：执行用于将由低于期望阈值电压的阈值电压定义的数据写入第一存储单元的第一数据写入操作; 执行用于将数据写入第二存储单元的第二数据写入操作; 以及执行用于将由所述期望阈值电压定义的数据写入所述第一存储单元的第三数据写入操作。

7. 发明授权

US08593880B2 Semiconductor memory system including a plurality of semiconductor memory devices 有权
标题翻译：半导体存储器系统包括多个半导体存储器件
公开(公告)号：US08593880B2
公开(公告)日：2013-11-26
申请号：US13598099
申请日：2012-08-29
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.
摘要翻译：通信线路连接到第一和第二芯片，并保持在第一信号电平。监视电路将通信线路的信号电平从第一信号改变到第二信号电平，而第一和第二芯片中的一个使用大于参考电流的电流。当通信线路的信号电平为第二信号电平时，第一和第二芯片中的另一个被控制到等待状态，该等待状态不转移到使用大于参考电流的电流的操作状态。

8. 发明申请

US20090190399A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF CORRECTING A READ LEVEL PROPERLY 有权
标题翻译：可修正读取电平的半导体存储器件
公开(公告)号：US20090190399A1
公开(公告)日：2009-07-30
申请号：US12416750
申请日：2009-04-01
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/02 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3418 , G11C2211/5646 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.
摘要翻译：在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平第一存储器单元，然后读取第一存储器单元的阈值电平。存储部存储校正等级。

9. 发明授权

US07525839B2 Semiconductor memory device capable of correcting a read level properly 有权
标题翻译：能够正确地校正读取电平的半导体存储器件
公开(公告)号：US07525839B2
公开(公告)日：2009-04-28
申请号：US11753143
申请日：2007-05-24
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C7/10
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/12 , G11C16/26 , G11C16/3418 , G11C2211/5646 , G11C2211/565
摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.
摘要翻译：在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平第一存储器单元，然后读取第一存储器单元的阈值电平。存储部存储校正等级。

10. 发明授权

US07394691B2 Semiconductor memory device which prevents destruction of data 有权
标题翻译：防止数据破坏的半导体存储器件
公开(公告)号：US07394691B2
公开(公告)日：2008-07-01
申请号：US11498142
申请日：2006-08-03
申请人： Noboru Shibata , Hiroshi Sukegawa
发明人： Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34 , G11C7/00 , G11C29/00
CPC分类号： G11C11/5642 , G11C11/5628 , G11C16/0483
摘要： A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.
摘要翻译：每个存储n个值的多个存储单元（n是不小于3的自然数）以矩阵形式布置在存储单元阵列中，并且每个存储单元与字线和位线连接。每个存储单元通过第一写操作和第二写操作来存储n值数据。读取部分设置字线的电位，并从存储器单元阵列中的存储单元读取数据。如果由读取部分读取并写入第二写入操作的数据包括不可校正的错误，则当读取在第一写入操作中写入的数据时，控制部分改变提供给读取部分的字线的电位。

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