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1. 发明申请

US20060120162A1 Method of writing data to a semiconductor memory device 有权
公开(公告)号：US20060120162A1
公开(公告)日：2006-06-08
申请号：US11270499
申请日：2005-11-10
申请人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
发明人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/28 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648 , G11C2216/14
摘要： A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.

2. 发明授权

US07593267B2 Method of writing data to a semiconductor memory device 有权
标题翻译：将数据写入半导体存储器件的方法
公开(公告)号：US07593267B2
公开(公告)日：2009-09-22
申请号：US11832990
申请日：2007-08-02
申请人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
发明人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/28 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648 , G11C2216/14
摘要： A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.
摘要翻译：一种将数据写入具有存储单元的半导体存储器件的方法，每个存储器单元以非易失性方式存储由其阈值电压定义的数据，该器件具有彼此相邻布置的第一和第二存储器单元，以顺序写入该存储器单元该方法包括：执行用于将由低于期望阈值电压的阈值电压定义的数据写入第一存储单元的第一数据写入操作; 执行用于将数据写入第二存储单元的第二数据写入操作; 以及执行用于将由所述期望阈值电压定义的数据写入所述第一存储单元的第三数据写入操作。

3. 发明申请

US20070280000A1 METHOD OF WRITING DATA TO A SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：将数据写入半导体存储器件的方法
公开(公告)号：US20070280000A1
公开(公告)日：2007-12-06
申请号：US11832990
申请日：2007-08-02
申请人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
发明人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/28 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648 , G11C2216/14
摘要： A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.
摘要翻译：一种将数据写入具有存储单元的半导体存储器件的方法，每个存储器单元以非易失性方式存储由其阈值电压定义的数据，该器件具有彼此相邻布置的第一和第二存储器单元，以顺序写入该存储器单元该方法包括：执行用于将由低于期望阈值电压的阈值电压定义的数据写入第一存储单元的第一数据写入操作; 执行用于将数据写入第二存储单元的第二数据写入操作; 以及执行用于将由所述期望阈值电压定义的数据写入所述第一存储单元的第三数据写入操作。

4. 发明授权

US07257032B2 Method of writing data to a semiconductor memory device 有权
标题翻译：将数据写入半导体存储器件的方法
公开(公告)号：US07257032B2
公开(公告)日：2007-08-14
申请号：US11270499
申请日：2005-11-10
申请人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
发明人： Masaki Fujiu , Noboru Shibata , Hiroshi Sukegawa
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/28 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5648 , G11C2216/14
摘要： A method of writing data to a semiconductor memory device with memory cells, each of which stores data defined by threshold voltage thereof in a non-volatile manner, the device having first and second memory cells disposed adjacent to each other to be sequentially written in this order, the method including: performing a first data write operation for writing data defined by a threshold voltage lower than a desired threshold voltage into the first memory cell; performing a second data write operation for writing data into the second memory cell; and performing a third data writing operation for writing data defined by the desired threshold voltage into the first memory cell.
摘要翻译：一种将数据写入具有存储单元的半导体存储器件的方法，每个存储器单元以非易失性方式存储由其阈值电压定义的数据，该器件具有彼此相邻布置的第一和第二存储器单元，以顺序写入该存储器单元该方法包括：执行用于将由低于期望阈值电压的阈值电压定义的数据写入第一存储单元的第一数据写入操作; 执行用于将数据写入第二存储单元的第二数据写入操作; 以及执行用于将由所述期望阈值电压定义的数据写入所述第一存储单元的第三数据写入操作。

5. 发明申请

US20130235662A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130235662A1
公开(公告)日：2013-09-12
申请号：US13607699
申请日：2012-09-08
申请人： Masaki Fujiu
发明人： Masaki Fujiu
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/0483
摘要： In one embodiment, a control circuit executes a first page writing operation, a first verify operations, a second page writing operation, a second verify operations, a step-up operation. The control circuit executes the first page writing operation which forms an intermediate distribution, and a first read operation which reads data form the intermediate distribution by using a determine voltage higher than a first verify voltage with a first value, and changes a second verify voltage based on the result of the first read operation.
摘要翻译：在一个实施例中，控制电路执行第一页写入操作，第一验证操作，第二页写入操作，第二验证操作，升压操作。控制电路执行形成中间分布的第一页写入操作和通过使用高于具有第一值的第一验证电压的确定电压从中间分布读取数据的第一读取操作，并且基于对第一次读取操作的结果。

6. 发明授权

US08203877B2 Non-volatile semiconductor memory device capable of preventing over-programming 有权
标题翻译：能够防止过度编程的非易失性半导体存储器件
公开(公告)号：US08203877B2
公开(公告)日：2012-06-19
申请号：US12884594
申请日：2010-09-17
申请人： Masaki Fujiu , Yoshikazu Harada
发明人： Masaki Fujiu , Yoshikazu Harada
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3468 , G11C16/3486 , G11C2211/5644
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a data memory circuit, a power generation circuit, and a controller. In the memory cell array, a plurality of memory cells which store two-or-more-bit data are arrayed in a matrix. When data is written to all memory cells connected to selected word lines, the controller performs a write operation with a write voltage obtained by adding the step-up voltage to the write voltage until a write count indicating a number of times by which writing is performed reaches a first write count. When the first write count is exceeded, the controller controls whether the step-up voltage is to be added or not, for each write operation.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，数据存储电路，发电电路和控制器。在存储单元阵列中，存储两位或多位数据的多个存储单元被排列成矩阵。当将数据写入连接到选定字线的所有存储单元时，控制器通过将升压电压加到写入电压而获得的写入电压进行写入操作，直到写入计数指示进行写入的次数达到第一个写入数。当超过第一次写入计数时，控制器控制是否对每个写入操作添加升压电压。

7. 发明申请

US20110063911A1 SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：US20110063911A1
公开(公告)日：2011-03-17
申请号：US12951616
申请日：2010-11-22
申请人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
发明人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
IPC分类号： G11C16/04 , G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.

8. 发明授权

US08184484B2 Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device 有权
标题翻译：半导体存储器件包括具有电荷累积层和控制栅极的堆叠栅极以及将数据写入半导体存储器件的方法
公开(公告)号：US08184484B2
公开(公告)日：2012-05-22
申请号：US13182847
申请日：2011-07-14
申请人： Masaki Fujiu
发明人： Masaki Fujiu
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.
摘要翻译：半导体存储器件包括存储单元，字线，驱动电路和控制电路。驱动器电路重复编程操作，其选择任何一条字线，将第一电压施加到选定的一条字线，以及将第二电压施加到未选择的一条字线，以将数据写入到所述存储器单元连接到所选择的一条字线。控制电路在驱动电路重复编程操作时，升高第一电压并保持第二电压恒定，直到第一电压达到第一阈值。控制电路在第一电压达到第一阈值之后升高第二电压。

9. 发明授权

US08023331B2 Semiconductor memory device including stacked gate having charge accumulation layer and control gate and method of writing data to semiconductor memory device 有权
公开(公告)号：US08023331B2
公开(公告)日：2011-09-20
申请号：US13030770
申请日：2011-02-18
申请人： Masaki Fujiu
发明人： Masaki Fujiu
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
摘要： A semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The driver circuit repeats a programming operation of selecting any one of the word lines, of applying a first voltage to selected one of the word lines, and of applying a second voltage to unselected one of the word lines, to write data to selected one of the memory cells connected to the selected one of the word lines. The control circuit, while the driver circuit is repeating the programming operation, steps up the first voltage and keeps the second voltage constant until the first voltage reaches a first threshold. The control circuit steps up the second voltage after the first voltage has reached the first threshold.

10. 发明授权

US08036038B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08036038B2
公开(公告)日：2011-10-11
申请号：US12951616
申请日：2010-11-22
申请人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
发明人： Makoto Iwai , Kazuhisa Kanazawa , Hiroshi Nakamura , Masaki Fujiu
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction.
摘要翻译：半导体存储器件包括存储单元阵列，其包括多个块，每个块包括存储单元单元和选择存储单元单元的选择晶体管;以及行解码器，包括第一块选择器和第二块选择器，每个块选择器包括多个传输晶体管，其被形成为对应于多个块并且在字线方向上彼此相邻布置，其中扩散层在第一块选择器和第二块选择器中形成为彼此相对，并且使第一块选择器的扩散层与字线方向上彼此相邻的第二块选择器之间的宽度大于与第一块选择器和第二块选择器相邻的第一块选择器和第二块选择器中的每一个中的扩散层之间的宽度其他在字线方向。

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