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1. 发明授权

US09112471B1 Gain control system for wireless communication system 有权
标题翻译：无线通信系统增益控制系统
公开(公告)号：US09112471B1
公开(公告)日：2015-08-18
申请号：US14218996
申请日：2014-03-19
申请人： Nitin Jain , Gopikrishna Charipadi
发明人： Nitin Jain , Gopikrishna Charipadi
IPC分类号： H04L27/08 , H03G3/30
CPC分类号： H03G3/3036 , H03G3/3052
摘要： A gain control system for a gain stage of a wireless communication system includes a gain control module and a mode selection module. The gain control module is operable in automatic gain control (AGC) and manual gain control (MGC) modes. The mode selection module checks the presence of first user-data in the first sub-frame based on a received signal strength indication (RSSI) value and/or a decibel amplitude level relative to full scale (dBFS) value, the presence of second user-data in a second sub-frame subsequent to the first sub-frame based on an advance information, calculates an estimated signal power level, and configures the gain control module in one of the AGC and MGC modes. Based on the mode, the gain control module provides a gain value to the gain stage.
摘要翻译：用于无线通信系统的增益级的增益控制系统包括增益控制模块和模式选择模块。增益控制模块可在自动增益控制（AGC）和手动增益控制（MGC）模式下工作。模式选择模块基于接收信号强度指示（RSSI）值和/或相对于满量程（dBFS）值的分贝幅度水平来检查第一子帧中的第一用户数据的存在，第二用户的存在基于提前信息在第一子帧之后的第二子帧中计算估计信号功率电平，并将增益控制模块配置为AGC和MGC模式之一。基于该模式，增益控制模块向增益级提供增益值。

2. 发明授权

US08743691B2 Priority aware MAC flow control 有权
标题翻译：优先级感知MAC流量控制
公开(公告)号：US08743691B2
公开(公告)日：2014-06-03
申请号：US13161439
申请日：2011-06-15
申请人： Nitin Jain , Rajkumar Jalan
发明人： Nitin Jain , Rajkumar Jalan
IPC分类号： H04L12/28 , H04L12/56 , G06F15/16 , G06F15/173
CPC分类号： H04L47/10 , G06F15/17368 , H04L12/2852 , H04L47/2433
摘要： Solutions are provided that allow a network device to apply flow control on the MAC layer while taking into account the priority of the frame of traffic. This may be accomplished by generating a frame indicating that traffic flow should be paused, while utilizing a new opcode value, or alternatively by utilizing a new type/length value (possibly combined with a new opcode value). A receiving device may then examine the fields of the frame to determine whether it should use priority-based pausing, and then examine other fields to determine which priority-levels to pause and for how long. This allows for improved efficiency in flow control on the MAC layer.
摘要翻译：提供的解决方案允许网络设备在考虑到流量帧的优先级的情况下对MAC层应用流量控制。这可以通过生成指示业务流应该被暂停，同时利用新的操作码值，或者通过利用新的类型/长度值（可能与新的操作码值组合）来实现。然后，接收设备可以检查帧的字段以确定它是否应该使用基于优先级的暂停，然后检查其他字段以确定要暂停的优先级等级以及多长时间。这样可以提高MAC层的流量控制效率。

3. 发明授权

US08520564B1 Integrated RF transceiver 有权
标题翻译：集成RF收发器
公开(公告)号：US08520564B1
公开(公告)日：2013-08-27
申请号：US13224798
申请日：2011-09-02
申请人： Shawn M. Lorg , Kenneth V. Buer , Ramana Darapu , Nitin Jain
发明人： Shawn M. Lorg , Kenneth V. Buer , Ramana Darapu , Nitin Jain
IPC分类号： H04B1/44
CPC分类号： H03G3/3042
摘要： The present disclosure includes an integrated full-duplex transceiver, which may be implemented on a single substrate or die. A single substrate may in turn, comprise, an I/O port configured for full-duplex operation, a transmit portion and a receive portion, a first mixer for up-converting a transmit signal, a second mixer for down-converting a receive signal, a first independently tunable local oscillator that drives the first mixer, and a second independently tunable local oscillator that drives the second mixer. The first independently tunable oscillator may facilitate up-conversion of a transmit IF signal, while a second independently tunable oscillator may facilitate down-conversion of a receive RF signal.
摘要翻译：本公开包括可以在单个基板或管芯上实现的集成全双工收发器。单个衬底可以依次包括被配置用于全双工操作的I / O端口，发送部分和接收部分，用于上变频发送信号的第一混频器，用于下变频接收信号的第二混频器，驱动第一混频器的第一独立可调谐本地振荡器，以及驱动第二混频器的第二独立可调谐本地振荡器。第一独立可调谐振荡器可以促进发射IF信号的上变频，而第二独立可调振荡器可以促进接收RF信号的下变频。

4. 发明申请

US20130208616A1 METHOD AND SYSTEM OF PROVIDING MDT MEASUREMENT INFORMATION TO A BASE STATION IN A WIRELESS NETWORK ENVIRONMENT 有权
标题翻译：在无线网络环境中向基站提供MDT测量信息的方法和系统
公开(公告)号：US20130208616A1
公开(公告)日：2013-08-15
申请号：US13878156
申请日：2011-10-05
申请人： Balaji Srinivasan Thiruvenkatachari , Himke Van Der Velde , Nitin Jain , Prateek Basu Mallick
发明人： Balaji Srinivasan Thiruvenkatachari , Himke Van Der Velde , Nitin Jain , Prateek Basu Mallick
IPC分类号： H04W24/10
CPC分类号： H04W24/10 , H04W16/18 , H04W88/02
摘要： The present invention provides a method and system of providing minimization drive test (MDT) measurement information to a base station in a wireless communication network. In one embodiment, a method includes indicating availability of MDT measurement information logged by user equipment to a base station in a wireless network environment. The method further includes receiving an information request message to transfer the MDT measurement information in response to the indication. The method includes transmitting an information response message including at least a portion of the MDT measurement information to the base station, where the information response message indicates whether any portion of MDT measurement information is leftover with the user equipment. The method then includes repeating the above steps of receiving and transmitting till the entire MDT measurement information is transferred to the base station.
摘要翻译：本发明提供了一种向无线通信网络中的基站提供最小化驱动测试（MDT）测量信息的方法和系统。在一个实施例中，一种方法包括在无线网络环境中指示用户设备向基站记录的MDT测量信息的可用性。该方法还包括接收信息请求消息以响应于该指示传送MDT测量信息。该方法包括向基站发送包括至少一部分MDT测量信息的信息响应消息，其中信息响应消息指示MDT测量信息的任何部分是否与用户设备一起残留。该方法然后包括重复上述接收和发送步骤，直到整个MDT测量信息被传送到基站。

5. 发明授权

US08458545B2 Method and apparatus for testing of a memory with redundancy elements 有权
标题翻译：用冗余元素测试存储器的方法和装置
公开(公告)号：US08458545B2
公开(公告)日：2013-06-04
申请号：US12955354
申请日：2010-11-29
申请人： Tanmoy Roy , Harsh Rawat , Swapnil Bahl , Amit Chhabra , Nitin Jain , Jatin Fultaria
发明人： Tanmoy Roy , Harsh Rawat , Swapnil Bahl , Amit Chhabra , Nitin Jain , Jatin Fultaria
IPC分类号： G01R31/28
CPC分类号： G11C29/42 , G11C29/024
摘要： A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.
摘要翻译：电路包括被配置为接收测试地址输入信号的输入节点和经配置以从测试地址输入信号的第一部分产生选择要测试的电路的第一部分的第一地址的第一地址信号的电路并且还从测试地址输入信号的第二部分生成被配置为选择要测试的电路的第二部分的第二信号。然后将测试电路配置为在测试模式下使用第一个地址和第二个部分。

6. 发明申请

US20130064185A1 METHOD AND SYSTEM FOR BULK ACTIVATION/DEACTIVATION OF COMPONENT CARRIERS IN A WIRELESS NETWORK ENVIRONMENT 有权
标题翻译：无线网络环境中组件运营商的大容量激活/消除方法与系统
公开(公告)号：US20130064185A1
公开(公告)日：2013-03-14
申请号：US13697733
申请日：2011-05-13
申请人： Satish Nanjunda Swamy Jamadagni , Nitin Jain
发明人： Satish Nanjunda Swamy Jamadagni , Nitin Jain
IPC分类号： H04W72/00 , H04W68/00
CPC分类号： H04L5/001 , H04L5/0037 , H04L5/0042 , H04L5/0092 , H04L5/0098 , H04L27/0006
摘要： Method and apparatus are provided for communicating availability and removal of one or more CCs in a cell. The one or more CCs that are available in the cell of a wireless communication network are determined, or a need to release one or more CCs that are active in the cell of a wireless communication network is detected. Availability of or the need to release the one or more CCs in the cell is communicated to a plurality of mobile stations. Each of the plurality of mobile stations is allowed to use or de-activate the one or more CCs in the cell.
摘要翻译：提供了用于传送单元中的一个或多个CC的可用性和移除的方法和装置。确定在无线通信网络的小区中可用的一个或多个CC，或者检测到需要释放在无线通信网络的小区中活动的一个或多个CC。将释放单元中的一个或多个CC的可用性或需要传送到多个移动站。允许多个移动站中的每一个使用或去激活小区中的一个或多个CC。

7. 发明申请

US20120169393A1 PROCESSING CLOCK SIGNALS 有权
标题翻译：处理时钟信号
公开(公告)号：US20120169393A1
公开(公告)日：2012-07-05
申请号：US12982593
申请日：2010-12-30
申请人： Nitin Gupta , Nitin Jain
发明人： Nitin Gupta , Nitin Jain
IPC分类号： H03K3/356 , H03K3/286 , H03K3/00
CPC分类号： H03K5/151 , H03K2005/00136
摘要： A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.
摘要翻译：一种用于处理包括不同极性的第一和第二时钟沿的时钟信号的电路，所述电路包括用于反相第一时钟沿以产生反相第一时钟沿的反相器，并且反相第二时钟沿以产生反相第二时钟沿; 第一通路门，用于接收反相时钟沿并输出第一极性的第一触发信号; 以及第二通路门，用于接收第二时钟沿并输出第一极性的第二触发信号，其中第二通道门被控制为响应于反相的第二时钟沿打开; 由此第一时钟沿和第一触发信号之间的延迟基本上等于第二时钟沿和第二触发信号之间的延迟。

8. 发明申请

US20120140582A1 WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURES 有权
标题翻译：用于分层存储器架构的写入电路
公开(公告)号：US20120140582A1
公开(公告)日：2012-06-07
申请号：US13370035
申请日：2012-02-09
申请人： Siddharth GUPTA , Nitin Jain , Anand Mishra
发明人： Siddharth GUPTA , Nitin Jain , Anand Mishra
IPC分类号： G11C7/00
CPC分类号： G11C7/1096 , G11C7/18 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/413
摘要： A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.
摘要翻译：存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给选择本地输入和输出电路。

9. 发明申请

US20120078995A1 SYSTEM AND METHOD FOR WARMING AN OPTIMIZATION DEVICE 审中-公开
标题翻译：用于加热优化装置的系统和方法
公开(公告)号：US20120078995A1
公开(公告)日：2012-03-29
申请号：US12893894
申请日：2010-09-29
申请人： Nitin Jain , Nandan Tammineedi , Gabriel Levy , Prashant Murthy , Charles Fraleigh , Sumanth Sukumar , Guy Messalem , Zhen Xue
发明人： Nitin Jain , Nandan Tammineedi , Gabriel Levy , Prashant Murthy , Charles Fraleigh , Sumanth Sukumar , Guy Messalem , Zhen Xue
IPC分类号： G06F15/16
CPC分类号： H04L67/2828 , H04L67/148 , H04L67/2876
摘要： A system and method are provided for warming a network intermediary (e.g., a proxy, a transaction accelerator) to enable it to provide effective optimization (e.g., data reduction) without a cold start. When a pair of network intermediaries cooperate to optimize a communication connection (e.g., between a client and a server), either or both intermediaries may form branch channels with one or more peers. Via these branch channels, the intermediaries may forward optimization information such as data references received from the other intermediary (i.e., in place of data segments, as part of a data reduction scheme), and/or resolve unknown references.
摘要翻译：提供了一种用于加热网络中介（例如，代理，事务加速器）以使其能够在没有冷启动的情况下提供有效优化（例如，数据简化）的系统和方法。当一对网络中介器协作以优化通信连接（例如，在客户端和服务器之间）时，任何一个或两个中间体可以与一个或多个对等体形成分支信道。通过这些分支信道，中介可以转发诸如从其他中间人接收的数据参考（即代替数据段，作为数据简化方案的一部分）的优化信息和/或解决未知参考。

10. 发明授权

US08130567B2 Write circuitry for hierarchical memory architecture 有权
标题翻译：写分层存储架构的电路
公开(公告)号：US08130567B2
公开(公告)日：2012-03-06
申请号：US12641102
申请日：2009-12-17
申请人： Siddharth Gupta , Nitin Jain , Anand Mishra
发明人： Siddharth Gupta , Nitin Jain , Anand Mishra
IPC分类号： G11C7/00
CPC分类号： G11C7/1096 , G11C7/18 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/413
摘要： A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.
摘要翻译：存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给选择本地输入和输出电路。

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