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1. 发明授权

US6026455A Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system 失效
标题翻译：用于为重试总线主机向计算机系统中连接两条总线的数据传输桥提供有保障的访问的架构和方法
公开(公告)号：US6026455A
公开(公告)日：2000-02-15
申请号：US201817
申请日：1994-02-24
申请人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
发明人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
IPC分类号： G06F13/40 , G06F13/36
CPC分类号： G06F13/4031
摘要： A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.
摘要翻译：适于与PCI和辅助总线电路相关联的桥接电路，桥接电路包括用于存储特定PCI总线主机尝试访问辅助总线并已被迫重试该接入的指示的电路，用于屏蔽的电路任何重试直到总线再次可用，以及用于提供间隔时间的电路，在该间隔期间，重试PCI总线主机被保证访问辅助总线，有利于在总线被放弃之后辅助总线上的总线主机，使得重试次序不会产生导致PCI总线带宽损失的操作。

2. 发明授权

US5664117A Apparatus and method for prefetching data to load buffers in a bridge between two buses in a computer 失效
标题翻译：用于预取数据以在计算机中的两条总线之间的桥中加载缓冲器的装置和方法
公开(公告)号：US5664117A
公开(公告)日：1997-09-02
申请号：US603688
申请日：1996-01-20
申请人： Nilesh Shah , Jasmin Ajanovic , Dahmane Dahmani
发明人： Nilesh Shah , Jasmin Ajanovic , Dahmane Dahmani
IPC分类号： G06F5/06 , G06F13/40 , G06F13/00
CPC分类号： G06F5/065 , G06F13/4059
摘要： A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus. Fetch circuitry fetches the requested data from the first bus and prefetches one or more additional data segments stored in memory locations sequentially following the memory location storing the requested data. The prefetched data segments are stored in a buffer for immediate access by subsequent data transfer requests. Supply circuitry transfers each data segment from the buffer to the second bus in response to receiving an address corresponding to the particular data segment on the address input circuitry.
摘要翻译：一种提供在计算机系统中的第一总线和第二总线之间有效数据传输的桥接电路。桥接电路接收指示存储要求从第一总线传送到第二总线的数据段的存储位置的地址。获取电路从第一总线获取所请求的数据，并且在存储所请求的数据的存储器位置之后顺序地预取存储在存储单元中的一个或多个附加数据段。预取的数据段存储在缓冲器中，以便通过后续数据传输请求立即访问。响应于接收到对应于地址输入电路上的特定数据段的地址，供应电路将每个数据段从缓冲器传送到第二总线。

3. 发明授权

US5519872A Fast address latch with automatic address incrementing 失效
标题翻译：快速地址锁存器，自动地址递增
公开(公告)号：US5519872A
公开(公告)日：1996-05-21
申请号：US175589
申请日：1993-12-30
申请人： Narendra Khandekar , Dahmane Dahmani , Jasmin Ajanovic
发明人： Narendra Khandekar , Dahmane Dahmani , Jasmin Ajanovic
IPC分类号： G06F13/42 , G06F13/364
CPC分类号： G06F13/4217
摘要： A latching mechanism captures an address transmitted on a multiplexed address/data bus and preserves it for the full bus cycle. A transparent latch with a multiplexed feedback path allows the address to be quickly captured and decoded. An additional multiplexer and latch cooperate with the first mentioned latch to keep the address stable for a sufficient time to allow latching by slower memory elements. Additional elements are provided to automatically increment the address for multiple data burst operation.
摘要翻译：锁存机制捕获在复用的地址/数据总线上发送的地址，并将其保留在整个总线周期。具有复用反馈路径的透明锁存器允许快速捕获和解码地址。一个附加的多路复用器和锁存器与第一个提到的锁存器配合，以保持地址稳定足够的时间以允许较慢存储器元件的锁存。提供附加元件以自动递增多个数据突发操作的地址。

4. 发明授权

US6112307A Method and apparatus for translating signals between clock domains of different frequencies 失效
标题翻译：用于在不同频率的时钟域之间翻译信号的方法和装置
公开(公告)号：US6112307A
公开(公告)日：2000-08-29
申请号：US552460
申请日：1995-11-09
申请人： Jasmin Ajanovic , Dahmane Dahmani , Kenneth Chris Holland , Narendra Khandekar
发明人： Jasmin Ajanovic , Dahmane Dahmani , Kenneth Chris Holland , Narendra Khandekar
IPC分类号： G06F1/12 , H04L7/00 , H04L7/02 , G06F1/08
CPC分类号： G06F1/12 , H04L7/0012 , H04L7/02
摘要： A synchronizing circuit translates signals in a slow clock domain into a fast clock domain. The frequency of the slow clock is a submultiple of the fast clock frequency. A synchronizing pulse signal is developed at the frequency of the slow clock, but is phase synchronized to the fast clock. The synchronizing pulse signal is employed to gate the signal in the slow clock domain so that it is synchronized in the fast clock domain. In a system where the ratio between the fast clock frequency and slow clock frequency is determined by a frequency divisor signal, a snooping circuit is employed to capture the frequency divisor signal to achieve rapid synchronization between the clock domains.
摘要翻译：同步电路将慢时钟域中的信号转换为快速时钟域。慢时钟频率是快时钟频率的一个倍数。在慢时钟的频率下产生同步脉冲信号，但是与快速时钟相位同步。采用同步脉冲信号对慢时钟域中的信号进行门控，使其在快速时钟域中同步。在快速时钟频率和慢时钟频率之间的比率由频率除数信号确定的系统中，采用窥探电路来捕获频率除数信号以实现时钟域之间的快速同步。

5. 发明授权

US5537664A Methods and apparatus for generating I/O recovery delays in a computer system 失效
标题翻译：在计算机系统中产生I / O恢复延迟的方法和装置
公开(公告)号：US5537664A
公开(公告)日：1996-07-16
申请号：US582664
申请日：1996-01-04
申请人： Stephen T. Rowland , Dahmane Dahmani
发明人： Stephen T. Rowland , Dahmane Dahmani
IPC分类号： G06F13/20
CPC分类号： G06F13/20
摘要： A computer system comprising programmable I/O recovery includes a device selection unit, programmable I/O recovery time registers, and a decrementer for specifying I/O recovery times for a plurality of I/O peripheral components. The programmable I/O recovery time registers contain time values, and the time values are programmable by the user of the computer system. The computer system interfaces the I/O peripheral components on an external bus through a plurality of bus cycle signals generated by cycle generation logic. For each I/O bus cycle on the external bus, the device selection unit identifies the I/O device involved in the I/O bus cycle. The device selection unit selects a time value from the programmable I/O recovery time registers corresponding to the I/O device identified, and loads the time value selected in the decrementer. Upon termination of the bus cycle, the device selection unit generates a cycle start signal to enable counting in the decrementer. The decrementer begins to count down from the time value loaded, and when the decrementer reaches a terminal count, a ready signal is generated. The ready signal enables the cycle generation logic to generate a successive bus cycle for the same I/O peripheral component.
摘要翻译：包括可编程I / O恢复的计算机系统包括设备选择单元，可编程I / O恢复时间寄存器和用于指定多个I / O外围组件的I / O恢复时间的减量器。可编程I / O恢复时间寄存器包含时间值，时间值可由计算机系统的用户编程。计算机系统通过由循环生成逻辑生成的多个总线周期信号将外部总线上的I / O外围部件连接起来。对于外部总线上的每个I / O总线周期，器件选择单元识别I / O总线周期中涉及的I / O设备。设备选择单元从所识别的I / O设备对应的可编程I / O恢复时间寄存器中选择时间值，并加载在减法器中选择的时间值。在总线周期结束时，设备选择单元产生一个周期开始信号，以使能在递减器中进行计数。减法器从加载的时间值开始倒计时，并且当减量器到达终端计数时，生成就绪信号。就绪信号使循环生成逻辑能够为相同的I / O外围组件生成连续的总线周期。

6. 发明授权

US5794070A Method and apparatus for fast DMA transfer on an industry standard architecture (ISA) bus 失效
标题翻译：用于工业标准架构（ISA）总线上快速DMA传输的方法和装置
公开(公告)号：US5794070A
公开(公告)日：1998-08-11
申请号：US730777
申请日：1996-10-16
申请人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
发明人： Jeffrey L. Rabe , Dave Smyth , David D. Lent , Sathyamurthi Sadhasivan , Dahmane Dahmani , Stephen T. Rowland , James S. Coke , Mitchell W. Dale
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.
摘要翻译：计算机系统包括直接存储器访问（DMA）传送单元和通过外部总线耦合的多个DMA设备。 DMA传送单元为多个DMA设备实现DMA传输。 DMA传输单元包含DMA控制器，总线仲裁器和总线控制器。 DMA控制器和总线控制器产生一个两个时钟周期的DMA传输。为了实现双时钟周期DMA传输，请求的DMA设备与DMA控制器建立DMA传输，使得在第一时钟周期期间断言DACK＃信号。在第二个时钟周期内，DMA控制器设置存储器地址。在第三个时钟周期内，总线控制器转换外部总线上的命令信号。在断言命令信号时，有效数据在外部总线上被断言。对于需求和块模式操作，在两个时钟周期的DMA传输中执行额外的DMA传输。 DMA控制器和总线控制器也产生三个时钟周期的DMA传输。

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