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1. 发明授权

US06455205B1 Method and apparatus for determining phase shifts and trim masks for an integrated circuit 有权
标题翻译：用于确定集成电路的相移和修剪掩模的方法和装置
公开(公告)号：US06455205B1
公开(公告)日：2002-09-24
申请号：US10017357
申请日：2001-12-13
申请人： Nicolas Bailey Cobb , Kyohei Sakajiri
发明人： Nicolas Bailey Cobb , Kyohei Sakajiri
IPC分类号： G03H104
CPC分类号： G03F1/26 , G03F1/70 , G03F7/2026
摘要： A method and apparatus for deep sub-micron layout optimization is described. Components of an integrated circuit (IC) design (e.g., gates) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (e.g., a phase shift mask) is generated that includes the component to be manufactured using the phase shifting process. A second mask (e.g., a trim mask) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (e.g., a diffusion region) in a different layer of the integrated circuit layout than the structure (e.g., the gate) being created with the phase shifting process.
摘要翻译：描述了深亚微米布局优化的方法和装置。与不使用相移处理而制造的电路相比，可以使用相移过程来识别和制造集成电路（IC）设计（例如，门）的组件以改善电路密度和/或性能。在一个实施例中，产生包括使用相移处理来制造的部件的第一掩模（例如，相移掩模）。还产生第二掩模（例如，修剪掩模）以进一步处理使用第一掩模产生的结构。基于集成电路布局的不同层中的区域（例如，扩散区域）来定义两个掩模，而不是通过相移过程创建的结构（例如，栅极）。

2. 发明授权

US06335128B1 Method and apparatus for determining phase shifts and trim masks for an integrated circuit 有权
公开(公告)号：US06335128B1
公开(公告)日：2002-01-01
申请号：US09407447
申请日：1999-09-28
申请人： Nicolas Bailey Cobb , Kyohei Sakajiri
发明人： Nicolas Bailey Cobb , Kyohei Sakajiri
IPC分类号： G03F900
CPC分类号： G03F1/26 , G03F1/70 , G03F7/2026
摘要： A method and apparatus for deep sub-micron layout optimization is described. Components of an integrated circuit (IC) design (e.g., gates) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (e.g., a phase shift mask) is generated that includes the component to be manufactured using the phase shifting process. A second mask (e.g., a trim mask) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (e.g., a diffusion region) in a different layer of the integrated circuit layout than the structure (e.g., the gate) being created with the phase shifting process.

3. 发明申请

US20130104091A1 Tolerable Flare Difference Determination 有权
标题翻译：耐受性光斑差异测定
公开(公告)号：US20130104091A1
公开(公告)日：2013-04-25
申请号：US13279176
申请日：2011-10-21
申请人： SERGIY KOMIRENKO , Nicolas Bailey Cobb , Raghu Chalasani
发明人： SERGIY KOMIRENKO , Nicolas Bailey Cobb , Raghu Chalasani
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G03F1/70 , G03F7/70941
摘要： Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions.
摘要翻译：本发明的方面涉及用于补偿光刻工艺中用于待制造在晶片上的相同电路阵列的光斑效应的技术。根据本发明的各种实施方式，从相同电路的阵列中选择参考电路，并且基于闪光差分层和可容许的光斑差分层来确定不可耐受的光斑差区域。相同电路的阵列的光刻处理结果可以从参考电路和不可容忍的闪光差分区域得到。

4. 发明授权

US07434199B2 Dense OPC 有权
标题翻译：密集OPC
公开(公告)号：US07434199B2
公开(公告)日：2008-10-07
申请号：US11236208
申请日：2005-09-27
申请人： Nicolas Bailey Cobb , Dragos Dudau
发明人： Nicolas Bailey Cobb , Dragos Dudau
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F1/36 , G03F7/70441
摘要： A method of calculating process conditions for performing optical and process correction (OPC) or other resolution enhancement techniques on a layout design. Process conditions are estimated on a layout database on a substantially uniform grid. Contour curves are created from the estimated process conditions. The contour curves are then compared against the features in the layout to determine edge placement errors. From the edge placement errors, OPC or other corrections for the features can be made.
摘要翻译：一种在布局设计中计算用于执行光学和过程校正（OPC）或其他分辨率增强技术的处理条件的方法。过程条件在基本统一的网格上的布局数据库上进行估计。从估计的过程条件创建轮廓曲线。然后将轮廓曲线与布局中的特征进行比较，以确定边缘放置误差。从边缘放置错误，可以进行OPC或其他功能的修正。

5. 发明申请

US20070074143A1 Dense OPC 有权
标题翻译：密集OPC
公开(公告)号：US20070074143A1
公开(公告)日：2007-03-29
申请号：US11236208
申请日：2005-09-27
申请人： Nicolas Bailey Cobb , Dragos Dudau
发明人： Nicolas Bailey Cobb , Dragos Dudau
IPC分类号： G06F17/50 , G03F1/00 , G21K5/00 , G06F19/00
CPC分类号： G03F7/705 , G03F1/36 , G03F7/70441
摘要： A method of calculating process conditions for performing optical and process correction (OPC) or other resolution enhancement techniques on a layout design. Process conditions are estimated on a layout database on a substantially uniform grid. Contour curves are created from the estimated process conditions. The contour curves are then compared against the features in the layout to determine edge placement errors. From the edge placement errors, OPC or other corrections for the features can be made.
摘要翻译：一种在布局设计中计算用于执行光学和过程校正（OPC）或其他分辨率增强技术的处理条件的方法。过程条件在基本统一的网格上的布局数据库上进行估计。从估计的过程条件创建轮廓曲线。然后将轮廓曲线与布局中的特征进行比较，以确定边缘放置误差。从边缘放置错误，可以进行OPC或其他功能的修正。

6. 发明授权

US06467076B1 Method and apparatus for submicron IC design 有权
标题翻译：亚微米IC设计方法与装置
公开(公告)号：US06467076B1
公开(公告)日：2002-10-15
申请号：US09302700
申请日：1999-04-30
申请人： Nicolas Bailey Cobb
发明人： Nicolas Bailey Cobb
IPC分类号： G06F1750
CPC分类号： G03F7/70541 , G03F1/36 , G03F7/70441
摘要： The present invention beneficially provides an improved method and apparatus for designing submicron integrated circuits. A tag identifier is provided to an integrated circuit (IC) design. The tag identifier defines a set of properties for edge fragments. Edge fragments are tagged if they have the set of properties defined by the tag identifier. For instance, tag identifiers may define edge fragments that make up line ends or comers, or tag identifiers may define edge fragments that have predetermined edge placement errors. In various embodiments, functions can be performed on the tagged edge fragments. For instance, rule-based optical proximity correction (OPC) or model-based OPC can be performed on the tagged edge fragments. Other functions may mark tagged edge fragments in a visual display of the IC design, display the number of edge fragments having particular tags in a histogram, or identify particularly complex and error prone regions in the IC design.
摘要翻译：本发明有利地提供了一种用于设计亚微米集成电路的改进方法和装置。标签标识符被提供给集成电路（IC）设计。标签标识符定义边缘片段的一组属性。如果边缘片段具有由标签标识符定义的属性集，则会被标记。例如，标签标识符可以定义构成行尾或角落的边缘片段，或者标签标识符可以定义具有预定边缘放置错误的边缘片段。在各种实施例中，可以对标记的边缘片段执行功能。例如，可以对标记的边缘片段执行基于规则的光学邻近校正（OPC）或基于模型的OPC。其他功能可以在IC设计的可视显示中标记标记的边缘片段，在直方图中显示具有特定标签的边缘片段的数量，或者识别IC设计中特别复杂和易出错的区域。

7. 发明授权

US06249904B1 Method and apparatus for submicron IC design using edge fragment tagging to correct edge placement distortion 有权
标题翻译：用于亚微米IC设计的方法和装置，使用边缘片段标签来校正边缘放置失真
公开(公告)号：US06249904B1
公开(公告)日：2001-06-19
申请号：US09302557
申请日：1999-04-30
申请人： Nicolas Bailey Cobb
发明人： Nicolas Bailey Cobb
IPC分类号： G06F1750
CPC分类号： G03F7/70541 , G03F1/36 , G03F7/70441
摘要： The present invention beneficially provides an improved method and apparatus for designing submicron integrated circuits. A tag identifier is provided to an integrated circuit (IC) design. The tag identifier defines properties for edge fragments in the IC design having edge placement distortion due to the proximity of neighboring features. Edge fragments are tagged if they have the properties defined by the tag identifier. Arbitrary assist features are introduced for each tagged edge fragment. Model-based optical and process correction (OPC) is performed on the tagged edge fragments and the corresponding assist features.
摘要翻译：本发明有利地提供了一种用于设计亚微米集成电路的改进方法和装置。标签标识符被提供给集成电路（IC）设计。标签标识符定义了IC设计中边缘片段的属性，由于邻近特征的邻近性，边缘放置失真。如果边缘片段具有由标签标识符定义的属性，则会对其进行标记。为每个标记的边缘片段引入任意辅助功能。对标记的边缘片段和相应的辅助特征进行基于模型的光学和过程校正（OPC）。

8. 发明授权

US08533636B2 Tolerable flare difference determination 有权
标题翻译：容忍眩光差异测定
公开(公告)号：US08533636B2
公开(公告)日：2013-09-10
申请号：US13279176
申请日：2011-10-21
申请人： Sergiy Komirenko , Nicolas Bailey Cobb , Raghu Chalasani
发明人： Sergiy Komirenko , Nicolas Bailey Cobb , Raghu Chalasani
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36 , G03F1/70 , G03F7/70941
摘要： Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions.
摘要翻译：本发明的方面涉及用于补偿光刻工艺中用于待制造在晶片上的相同电路阵列的光斑效应的技术。根据本发明的各种实施方式，从相同电路的阵列中选择参考电路，并且基于闪光差分层和可容许的光斑差分层来确定不可耐受的光斑差区域。相同电路的阵列的光刻处理结果可以从参考电路和不可容忍的闪光差分区域得到。

9. 发明授权

US07367009B2 Convergence technique for model-based optical and process correction 有权
标题翻译：基于模型的光学和过程校正的收敛技术
公开(公告)号：US07367009B2
公开(公告)日：2008-04-29
申请号：US11388783
申请日：2006-03-24
申请人： Nicolas Bailey Cobb , Emile Sahouria
发明人： Nicolas Bailey Cobb , Emile Sahouria
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/70 , G06F17/5081
摘要： Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.
摘要翻译：布局校正使用前向映射技术完成。前向映射是指从标线布局到目标布局的片段映射，而反向映射是指从目标布局到标线布局的片段映射。前向映射提供了一种技术，用于对每个标线片段进行明确的映射到相应的目标布局片段。映射不一定提供标线片段和目标布局片段之间的一一对应关系。也就是说，多个标线布局片段可以映射到单个目标布局片段。使用目标布局片段的边缘放置错误来对相应的掩模版片段进行定位校正。边缘放置误差可以例如通过模拟使用标线的制造过程的模拟过程来确定。

10. 发明授权

US06430737B1 Convergence technique for model-based optical and process correction 有权
标题翻译：基于模型的光学和过程校正的收敛技术
公开(公告)号：US06430737B1
公开(公告)日：2002-08-06
申请号：US09613214
申请日：2000-07-10
申请人： Nicolas Bailey Cobb , Emile Sahouria
发明人： Nicolas Bailey Cobb , Emile Sahouria
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F1/70 , G06F17/5081
摘要： Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.
摘要翻译：布局校正使用前向映射技术完成。前向映射是指从标线布局到目标布局的片段映射，而反向映射是指从目标布局到标线布局的片段映射。前向映射提供了一种技术，用于对每个标线片段进行明确的映射到相应的目标布局片段。映射不一定提供标线片段和目标布局片段之间的一一对应关系。也就是说，多个标线布局片段可以映射到单个目标布局片段。使用目标布局片段的边缘放置错误来对相应的掩模版片段进行定位校正。边缘放置误差可以例如通过模拟使用标线的制造过程的模拟过程来确定。

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