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1. 发明申请

US20090092799A1 MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER 有权
标题翻译：具有双重电阻和单模式传输的混合光刻
公开(公告)号：US20090092799A1
公开(公告)日：2009-04-09
申请号：US11867428
申请日：2007-10-04
申请人： Nicholas C. Fuller , Michael A. Guillorn , Balasubramanian S. Pranatharthi Haran , Jyotica V. Patel
发明人： Nicholas C. Fuller , Michael A. Guillorn , Balasubramanian S. Pranatharthi Haran , Jyotica V. Patel
IPC分类号： G03C5/00 , G03G7/00
CPC分类号： G03F7/0035 , Y10S430/143 , Y10T428/24612 , Y10T428/24802
摘要： An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.
摘要翻译：在碳基材料层或下层上形成无机电子束敏感氧化物层。无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上，随后用紫外线照射并显影。图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中，随后进入下层以形成沟槽。碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模，并且之后可以容易地剥离。随后去除图案化的紫外线敏感光刻胶，图案化氧化物区域和图案化的碳基材料层。

2. 发明授权

US08334090B2 Mixed lithography with dual resist and a single pattern transfer 有权
标题翻译：具有双光栅和单一图案转印的混合光刻
公开(公告)号：US08334090B2
公开(公告)日：2012-12-18
申请号：US13015668
申请日：2011-01-28
申请人： Nicholas C. Fuller , Michael A. Guillorn , Balasubramanian S. Pranatharthi Haran , Jyotica V. Patel
发明人： Nicholas C. Fuller , Michael A. Guillorn , Balasubramanian S. Pranatharthi Haran , Jyotica V. Patel
IPC分类号： G03C5/00
CPC分类号： G03F7/0035 , Y10S430/143 , Y10T428/24612 , Y10T428/24802
摘要： An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.
摘要翻译：在碳基材料层或下层上形成无机电子束敏感氧化物层。无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上，随后用紫外线照射并显影。图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中，随后进入下层以形成沟槽。碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模，并且之后可以容易地剥离。随后去除图案化的紫外线敏感光刻胶，图案化氧化物区域和图案化的碳基材料层。

3. 发明申请

US20110123779A1 MIXED LITHOGRAPHY WITH DUAL RESIST AND A SINGLE PATTERN TRANSFER 有权
标题翻译：具有双重电阻和单模式传输的混合光刻
公开(公告)号：US20110123779A1
公开(公告)日：2011-05-26
申请号：US13015668
申请日：2011-01-28
申请人： Nicholas C. Fuller , Michael A. Guillorn , Balasubramanian S. Pranatharthi Haran , Jyotica V. Patel
发明人： Nicholas C. Fuller , Michael A. Guillorn , Balasubramanian S. Pranatharthi Haran , Jyotica V. Patel
IPC分类号： B32B3/10
CPC分类号： G03F7/0035 , Y10S430/143 , Y10T428/24612 , Y10T428/24802
摘要： An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.
摘要翻译：在碳基材料层或下层上形成无机电子束敏感氧化物层。无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上，随后用紫外线照射并显影。图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中，随后进入下层以形成沟槽。碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模，并且之后可以容易地剥离。随后去除图案化的紫外线敏感光刻胶，图案化氧化物区域和图案化的碳基材料层。

4. 发明授权

US07914970B2 Mixed lithography with dual resist and a single pattern transfer 有权
标题翻译：具有双光栅和单一图案转印的混合光刻
公开(公告)号：US07914970B2
公开(公告)日：2011-03-29
申请号：US11867428
申请日：2007-10-04
申请人： Nicholas C. Fuller , Michael A. Guillorn , Balasubramanian S. Pranatharthi Haran , Jyotica V. Patel
发明人： Nicholas C. Fuller , Michael A. Guillorn , Balasubramanian S. Pranatharthi Haran , Jyotica V. Patel
IPC分类号： G03C5/00
CPC分类号： G03F7/0035 , Y10S430/143 , Y10T428/24612 , Y10T428/24802
摘要： An inorganic electron beam sensitive oxide layer is formed on a carbon based material layer or an underlying layer. The inorganic electron beam sensitive oxide layer is exposed with an electron beam and developed to form patterned oxide regions. An ultraviolet sensitive photoresist layer is applied over the patterned oxide regions and exposed surfaces of the carbon based material layer, and subsequently exposed with an ultraviolet radiation and developed. The combined pattern of the patterned ultraviolet sensitive photoresist and the patterned oxide regions is transferred into the carbon based material layer, and subsequently into the underlying layer to form trenches. The carbon based material layer serves as a robust mask for performing additional pattern transfer into the underlying layer, and may be easily stripped afterwards. The patterned ultraviolet sensitive photoresist, the patterned oxide regions, and the patterned carbon based material layer are subsequently removed.
摘要翻译：在碳基材料层或下层上形成无机电子束敏感氧化物层。无机电子束敏感氧化层用电子束曝光并显影以形成图案化氧化物区域。将紫外线敏感的光致抗蚀剂层施加在图案化的氧化物区域和碳基材料层的暴露表面上，随后用紫外线照射并显影。图案化紫外光敏光致抗蚀剂和图案化氧化物区域的组合图案被转移到碳基材料层中，随后进入下层以形成沟槽。碳基材料层用作用于执行额外图案转移到下层中的鲁棒掩模，并且之后可以容易地剥离。随后去除图案化的紫外线敏感光刻胶，图案化氧化物区域和图案化的碳基材料层。

5. 发明申请

US20090174036A1 PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES 审中-公开
标题翻译：等离子体固化材料的等离子体刻蚀特性
公开(公告)号：US20090174036A1
公开(公告)日：2009-07-09
申请号：US11969525
申请日：2008-01-04
申请人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
发明人： Nicholas C. Fuller , Michael A. Guillorn , Hirohisa Kawasaki , Atsushi Yagishita
IPC分类号： H01L29/30 , G03F7/26
CPC分类号： G03F7/40
摘要： A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.
摘要翻译：公开了一种能够在光刻图案化之后显着降低线边缘粗糙度（LER）和线宽粗糙度（LEW）来制造半导体器件（即STI结构，栅极和互连）的方法。本发明的方法需要使用含有等离子体的惰性物质来调整光刻后的真空紫外（VUV）发射和/或给定特征（在相同的蚀刻平台上）的一个蚀刻工艺，以引发增加的交联的一个或多个图案形成材料，因此能够提高耐蚀刻性和减少LER和LEW后蚀刻处理。

6. 发明授权

US08754530B2 Self-aligned borderless contacts for high density electronic and memory device integration 有权
标题翻译：用于高密度电子和存储器件集成的自对准无边界触点
公开(公告)号：US08754530B2
公开(公告)日：2014-06-17
申请号：US12193339
申请日：2008-08-18
申请人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
发明人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
IPC分类号： H01L23/48
CPC分类号： H01L21/76897 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.
摘要翻译：公开了一种制造具有自对准无边界电触头的晶体管的方法。栅极堆叠形成在硅区域上。在栅堆叠周围形成偏置的间隔物。包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。在牺牲层中限定图案以限定电接触的接触面积。该图案暴露了栅极堆叠和源极/漏极的至少一部分。沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。已经定义的高度的接触面积被金属化以形成电接触。

7. 发明申请

US20100038723A1 SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION 有权
标题翻译：用于高密度电子和存储器件集成的自对准无边界联系
公开(公告)号：US20100038723A1
公开(公告)日：2010-02-18
申请号：US12193339
申请日：2008-08-18
申请人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
发明人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L21/76897 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.
摘要翻译：公开了一种制造具有自对准无边界电触头的晶体管的方法。栅极堆叠形成在硅区域上。在栅堆叠周围形成偏置的间隔物。包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。在牺牲层中限定图案以限定电接触的接触面积。该图案暴露了栅极堆叠和源极/漏极的至少一部分。沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。已经定义的高度的接触面积被金属化以形成电接触。

8. 发明授权

US08159042B2 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US08159042B2
公开(公告)日：2012-04-17
申请号：US12144229
申请日：2008-06-23
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

9. 发明申请

US20110278580A1 METHODOLOGY FOR FABRICATING ISOTROPICALLY SOURCE REGIONS OF CMOS TRANSISTORS 审中-公开
标题翻译：制造CMOS晶体管等电源区的方法
公开(公告)号：US20110278580A1
公开(公告)日：2011-11-17
申请号：US12779079
申请日：2010-05-13
申请人： Nicholas C. Fuller , Steve Koester , Isaac Lauer , Ying Zhang
发明人： Nicholas C. Fuller , Steve Koester , Isaac Lauer , Ying Zhang
IPC分类号： H01L29/78 , H01L29/06 , H01L29/04 , H01L21/311
CPC分类号： H01L29/78675 , H01L21/3065 , H01L21/3083 , H01L21/84 , H01L29/66636 , H01L29/66659 , H01L29/7848 , H01L29/78618 , H01L29/78654
摘要： A method for fabricating recessed source regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.
摘要翻译：一种用于制造积极缩放CMOS器件的凹陷源区的方法。在该方法中，使用等离子体蚀刻，沉积，随后进行等离子体蚀刻的处理顺序可控制地在薄体的沟道中形成远远小于40nm的器件的源极的凹陷区域，以使SiGe，SiC的后续外延生长，或其他材料，并且随之而来的器件和环形振荡器性能的增加。还提供场效应晶体管器件，其包括：掩埋氧化物层; 掩埋氧化物层上方的硅层; 各向同性凹陷的源区; 以及包括栅极电介质，导电材料和间隔物的栅极堆叠。

10. 发明授权

US07196014B2 System and method for plasma induced modification and improvement of critical dimension uniformity 有权
标题翻译：用于等离子体诱导修饰和改善临界尺寸均匀性的系统和方法
公开(公告)号：US07196014B2
公开(公告)日：2007-03-27
申请号：US10983345
申请日：2004-11-08
申请人： Timothy J. Dalton , Ronald A. Della Guardia , Nicholas C. Fuller
发明人： Timothy J. Dalton , Ronald A. Della Guardia , Nicholas C. Fuller
IPC分类号： H01L21/311
CPC分类号： H01L21/31138 , G03F7/40 , G03F7/405 , H01L21/0276 , H01L21/31144
摘要： Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved device performance, functionality and reliability.
摘要翻译：具有OSG或聚合物（90nm及以上的BEOL技术）的新型互连结构，其中采用先进的等离子体处理以减少半导体器件中的后平版印刷光盘不均匀性（“线边缘粗糙度”）。新颖的互连结构具有增强的衬垫和种子保形性，因此能够提供改进的设备性能，功能性和可靠性。

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