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1. 发明申请

US20080080809A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20080080809A1
公开(公告)日：2008-04-03
申请号：US11906725
申请日：2007-10-03
申请人： Natsuki Kushiyama , Yukihiro Urakawa
发明人： Natsuki Kushiyama , Yukihiro Urakawa
IPC分类号： G02B6/12
CPC分类号： G02B6/12002 , G02B6/43 , G02B2006/12104 , G06F1/105
摘要： A semiconductor integrated circuit according to an example of the present invention includes a chip substrate, first and second switches arranged on the chip substrate in which ON/OFF of an electrical signal path is directly controlled by an optical signal, a first light shielding layer arranged above the chip substrate, an optical waveguide layer arranged on the first light shielding layer, a second light shielding layer arranged on the optical waveguide layer, a reflecting plate arranged in the optical waveguide layer to change an advancing direction of the optical signal, and means for leading the optical signal to the first and second switches from an inside of the optical waveguide layer. The first and second light shielding layers reflect the optical signal, and the optical waveguide layer transmits the optical signal radially.
摘要翻译：根据本发明的实施例的半导体集成电路包括芯片基板，布置在芯片基板上的第一和第二开关，其中电信号路径的导通/截止由光信号直接控制，第一遮光层布置在芯片基板的上方配置有布置在第一遮光层上的光波导层，布置在光波导层上的第二遮光层，布置在光波导层中以改变光信号的前进方向的反射板，用于将光信号从光波导层的内部引导到第一和第二开关。第一和第二遮光层反射光信号，并且光波导层径向透射光信号。

2. 发明申请

US20050134300A1 Semiconductor integrated circuit and method for testing a semiconductor integrated circuit 失效
标题翻译：半导体集成电路和半导体集成电路测试方法
公开(公告)号：US20050134300A1
公开(公告)日：2005-06-23
申请号：US11001155
申请日：2004-12-02
申请人： Natsuki Kushiyama , Yukihiro Urakawa
发明人： Natsuki Kushiyama , Yukihiro Urakawa
IPC分类号： G01R31/28 , G01R31/02 , G01R31/30 , G01R31/317 , H01L21/822 , H01L27/04
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.
摘要翻译：半导体集成电路包括产生第一延迟时钟的第一延迟电路; 产生第二延迟时钟的第二延迟电路; 注册第一延迟时钟的第一延迟值的第一寄存器; 第二寄存器，其记录所述第二延迟时钟的第二延迟值; 时钟供给电路，向第一和第二延迟电路提供时钟信号; 相位比较器，检测第一和第二延迟时钟之间的相位差; 以及内置测试电路，被配置为控制第一和第二寄存器，使得可以将第一延迟的值登记在第一寄存器中，并且可以将第二延迟的值登记在第二寄存器中。

3. 发明授权

US08867868B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08867868B2
公开(公告)日：2014-10-21
申请号：US11906725
申请日：2007-10-03
申请人： Natsuki Kushiyama , Yukihiro Urakawa
发明人： Natsuki Kushiyama , Yukihiro Urakawa
IPC分类号： G02B6/30 , G02B6/43 , G02B6/12 , G06F1/10
CPC分类号： G02B6/12002 , G02B6/43 , G02B2006/12104 , G06F1/105
摘要： A semiconductor integrated circuit according to an example of the present invention includes a chip substrate, first and second switches arranged on the chip substrate in which ON/OFF of an electrical signal path is directly controlled by an optical signal, a first light shielding layer arranged above the chip substrate, an optical waveguide layer arranged on the first light shielding layer, a second light shielding layer arranged on the optical waveguide layer, a reflecting plate arranged in the optical waveguide layer to change an advancing direction of the optical signal, and means for leading the optical signal to the first and second switches from an inside of the optical waveguide layer. The first and second light shielding layers reflect the optical signal, and the optical waveguide layer transmits the optical signal radially.
摘要翻译：根据本发明的实施例的半导体集成电路包括芯片基板，布置在芯片基板上的第一和第二开关，其中电信号路径的导通/截止由光信号直接控制，第一遮光层布置在芯片基板的上方配置有布置在第一遮光层上的光波导层，布置在光波导层上的第二遮光层，布置在光波导层中以改变光信号的前进方向的反射板，用于将光信号从光波导层的内部引导到第一和第二开关。第一和第二遮光层反射光信号，并且光波导层径向透射光信号。

4. 发明授权

US07251765B2 Semiconductor integrated circuit and method for testing a semiconductor integrated circuit 失效
标题翻译：半导体集成电路和半导体集成电路测试方法
公开(公告)号：US07251765B2
公开(公告)日：2007-07-31
申请号：US11001155
申请日：2004-12-02
申请人： Natsuki Kushiyama , Yukihiro Urakawa
发明人： Natsuki Kushiyama , Yukihiro Urakawa
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A semiconductor integrated circuit includes a first delay circuit generating a first delay clock; a second delay circuit generating a second delay clock; a first register registering a value of a first delay of the first delay clock; a second register registering a value of a second delay of the second delay clock; a clock supplying circuit supplying a clock signal to the first and second delay circuits; a phase comparator detecting a phase difference between the first and second delay clocks; and a built-in test circuit configured to control the first and second registers so that the value of the first delay can be registered in the first register and the value of the second delay can be registered in the second register.
摘要翻译：半导体集成电路包括产生第一延迟时钟的第一延迟电路; 产生第二延迟时钟的第二延迟电路; 注册第一延迟时钟的第一延迟值的第一寄存器; 第二寄存器，其记录所述第二延迟时钟的第二延迟值; 时钟供给电路，向第一和第二延迟电路提供时钟信号; 相位比较器，检测第一和第二延迟时钟之间的相位差; 以及内置测试电路，被配置为控制第一和第二寄存器，使得可以将第一延迟的值登记在第一寄存器中，并且可以将第二延迟的值登记在第二寄存器中。

5. 发明授权

US07657798B2 Semiconductor integrated circuit and the same checking method 失效
标题翻译：半导体集成电路和相同的检查方法
公开(公告)号：US07657798B2
公开(公告)日：2010-02-02
申请号：US11645509
申请日：2006-12-27
申请人： Natsuki Kushiyama , Shigeaki Iwasa
发明人： Natsuki Kushiyama , Shigeaki Iwasa
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/1004 , G11C11/41 , G11C29/02 , G11C29/027 , G11C2029/4402
摘要： A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses, a plurality of second fuses, a plurality of third fuses, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part that outputs information indicative of whether the first to third fuses are correctly programmed.
摘要翻译：半导体集成电路具有单元阵列，能够代替有缺陷单元的冗余单元，冗余控制电路，多个第一保险丝，多个第二保险丝，多个第三保险丝，配置成保持状态的第一移位寄存器多个第一保险丝的第二移位寄存器，第二移位寄存器，被配置为级联连接到第一移位寄存器并保持多个第二保险丝的状态;第三移位寄存器，被配置为级联连接到第一和第二移位寄存器并且保持多个第三熔丝的状态，CRC余数计算器被配置为顺序地将由第一至第三移位寄存器保持的信息输入到CRC生成方程式以计算通过除法获得的余数，以及CRC确定部分，其输出指示信息是否正确编程了第一至第三个保险丝。

6. 发明授权

US07538369B2 Resistance-change-type fuse circuit 失效
标题翻译：电阻变化型保险丝电路
公开(公告)号：US07538369B2
公开(公告)日：2009-05-26
申请号：US11741222
申请日：2007-04-27
申请人： Natsuki Kushiyama
发明人： Natsuki Kushiyama
IPC分类号： H01L27/10
CPC分类号： G11C17/18 , G11C5/147 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A resistance-change-type fuse circuit has a plurality of polysilicon fuses which are made of polysilicon and causes irreversible change in resistance by flowing a current; a plurality of programming transistors which are provided corresponding to the plurality of fuses, each programming transistor switching whether to flow the current through the corresponding fuse to cause change in resistance with respect to the polysilicon fuses, a dummy fuse group including a plurality of dummy fuses having the same electrical properties as that of the polysilicon fuses, each dummy fuse having 1/n (n is an integer equal to or more than 1) times a resistance of the polysilicon fuses, a dummy transistor circuit which has at least one of dummy transistor having 1/n times a conductance of the programming transistors, a gate and a drain of the dummy transistor being connected to each other, and a current mirror circuit including the programming transistor and the dummy transistor, the current mirror circuit causing each polysilicon fuse to flow n times the current flowing through the dummy fuse group.
摘要翻译：电阻变化型熔丝电路具有由多晶硅制成的多个多晶硅保险丝，通过流过电流而导致电阻的不可逆变化; 多个编程晶体管，其对应于多个保险丝设置，每个编程晶体管切换是否流过相应的熔丝以使电流相对于多晶硅熔丝引起电阻变化;虚拟熔丝组包括多个虚拟熔丝具有与多晶硅保险丝相同的电性能，每个虚拟熔丝具有多晶硅熔丝的电阻的1 / n（n是等于或大于1的整数）倍，具有至少一个虚拟的虚拟晶体管电路晶体管具有编程晶体管的导通的1 / n倍，虚设晶体管的栅极和漏极彼此连接，以及包括编程晶体管和虚设晶体管的电流镜电路，使得每个多晶硅熔丝流过虚拟熔断器组的电流n倍。

7. 发明申请

US20070009073A1 Data sampling circuit and semiconductor integrated circuit 失效
标题翻译：数据采样电路和半导体集成电路
公开(公告)号：US20070009073A1
公开(公告)日：2007-01-11
申请号：US11443184
申请日：2006-05-31
申请人： Natsuki Kushiyama
发明人： Natsuki Kushiyama
IPC分类号： H04L7/00 , H04L7/04
CPC分类号： H04L7/0337 , H04L7/0025
摘要： A data sampling circuit has a receiver which receives an embedded clock obtained by multiplexing a clock signal and data, a phase comparator which outputs a phase difference signal by performing a phase comparison between the embedded clock and a first reference clock signal, a phase interpolator which adjusts a phase of the first reference clock signal and generates a second reference clock signal having a phase different from the phase of the first reference clock signal by 90°, based on the phase difference signal, a feedback controller which conforms the phase of the first reference clock signal with the phase of the embedded clock by feedback control using the phase comparator and the phase interpolator, a sampling controller which performs phase interpolation of the second reference clock signal at higher speed than the feedback control of the first feedback loop based on the phase difference signal, and a sampling circuit which samples the embedded clock received by the receiver in synchronization with the second reference clock signal obtained by phase interpolation of the sampling controller.
摘要翻译：数据采样电路具有接收通过复用时钟信号和数据而获得的嵌入时钟的接收器，通过执行嵌入时钟与第一参考时钟信号之间的相位比较输出相位差信号的相位比较器，相位内插器，调整第一参考时钟信号的相位，并且基于相位差信号产生具有与第一参考时钟信号的相位相差90°的第二参考时钟信号，反馈控制器符合第一参考时钟信号的相位参考时钟信号，通过使用相位比较器和相位内插器的反馈控制，嵌入时钟的相位;采样控制器，其以比第一反馈回路的反馈控制更高的速度执行第二参考时钟信号的相位插值，相位差信号，以及采样电路，对由接收器接收的嵌入式时钟进行采样 r与通过采样控制器的相位插值获得的第二参考时钟信号同步。

8. 发明授权

US5532963A Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：US5532963A
公开(公告)日：1996-07-02
申请号：US523741
申请日：1995-09-05
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C29/02 , G11C29/24 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C11/401 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

9. 发明申请

US20110227609A1 SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF EVALUATING THE CHARACTERISTICS OF A TRANSISTOR 审中-公开
标题翻译：用于评估晶体管特性的半导体集成电路
公开(公告)号：US20110227609A1
公开(公告)日：2011-09-22
申请号：US13050078
申请日：2011-03-17
申请人： Natsuki Kushiyama
发明人： Natsuki Kushiyama
IPC分类号： H03K5/00 , H03L7/00
CPC分类号： H03K17/18 , G01R31/2884
摘要： According to one embodiment, a test circuit comprises a function block, a test circuit, and a signal generation circuit. The test circuit is arranged in an area close to the function block having a plurality of transistors. The test circuit comprises a first flip-flop circuit, a second flip-flop circuit, and a logic circuit connected between the output of the first flip-flop circuit and the input of the second flip-flop circuit. The signal generation circuit generates clock pulses including a first clock pulse and a second clock pulse. The signal generation circuit is capable of controlling a pulse interval between the first clock pulse and the second clock pulse. In a test, the first flip-flop circuit outputs data in synchronization with the first clock pulse of the signal generation circuit and the second flip-flop circuit latches data in synchronization with the second clock pulse of the signal generation circuit.
摘要翻译：根据一个实施例，测试电路包括功能块，测试电路和信号发生电路。测试电路布置在靠近具有多个晶体管的功能块的区域中。测试电路包括第一触发器电路，第二触发器电路和连接在第一触发器电路的输出端和第二触发器电路的输入端之间的逻辑电路。信号发生电路产生包括第一时钟脉冲和第二时钟脉冲的时钟脉冲。信号发生电路能够控制第一时钟脉冲和第二时钟脉冲之间的脉冲间隔。在测试中，第一触发器电路与信号产生电路的第一时钟脉冲同步输出数据，第二触发器电路与信号发生电路的第二时钟脉冲同步地锁存数据。

10. 发明授权

US07526049B2 Data sampling circuit and semiconductor integrated circuit 失效
标题翻译：数据采样电路和半导体集成电路
公开(公告)号：US07526049B2
公开(公告)日：2009-04-28
申请号：US11443184
申请日：2006-05-31
申请人： Natsuki Kushiyama
发明人： Natsuki Kushiyama
IPC分类号： H03D3/24
CPC分类号： H04L7/0337 , H04L7/0025
摘要： A data sampling circuit has a receiver which receives an embedded clock obtained by multiplexing a clock signal and data, a phase comparator which outputs a phase difference signal by performing a phase comparison between the embedded clock and a first reference clock signal, a phase interpolator which adjusts a phase of the first reference clock signal and generates a second reference clock signal having a phase different from the phase of the first reference clock signal by 90°, based on the phase difference signal, a feedback controller which conforms the phase of the first reference clock signal with the phase of the embedded clock by feedback control using the phase comparator and the phase interpolator, a sampling controller which performs phase interpolation of the second reference clock signal at higher speed than the feedback control of the first feedback loop based on the phase difference signal, and a sampling circuit which samples the embedded clock received by the receiver in synchronization with the second reference clock signal obtained by phase interpolation of the sampling controller.
摘要翻译：数据采样电路具有接收通过复用时钟信号和数据而获得的嵌入时钟的接收器，通过执行嵌入时钟与第一参考时钟信号之间的相位比较输出相位差信号的相位比较器，相位内插器，调整第一参考时钟信号的相位，并且基于相位差信号产生具有与第一参考时钟信号的相位相差90°的第二参考时钟信号，反馈控制器符合第一参考时钟信号的相位参考时钟信号，通过使用相位比较器和相位内插器的反馈控制，嵌入时钟的相位;采样控制器，其以比第一反馈回路的反馈控制更高的速度执行第二参考时钟信号的相位插值，相位差信号，以及采样电路，对由接收器接收的嵌入式时钟进行采样 r与通过采样控制器的相位插值获得的第二参考时钟信号同步。

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