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1. 发明授权

US07657798B2 Semiconductor integrated circuit and the same checking method 失效
标题翻译：半导体集成电路和相同的检查方法
公开(公告)号：US07657798B2
公开(公告)日：2010-02-02
申请号：US11645509
申请日：2006-12-27
申请人： Natsuki Kushiyama , Shigeaki Iwasa
发明人： Natsuki Kushiyama , Shigeaki Iwasa
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/1004 , G11C11/41 , G11C29/02 , G11C29/027 , G11C2029/4402
摘要： A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses, a plurality of second fuses, a plurality of third fuses, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part that outputs information indicative of whether the first to third fuses are correctly programmed.
摘要翻译：半导体集成电路具有单元阵列，能够代替有缺陷单元的冗余单元，冗余控制电路，多个第一保险丝，多个第二保险丝，多个第三保险丝，配置成保持状态的第一移位寄存器多个第一保险丝的第二移位寄存器，第二移位寄存器，被配置为级联连接到第一移位寄存器并保持多个第二保险丝的状态;第三移位寄存器，被配置为级联连接到第一和第二移位寄存器并且保持多个第三熔丝的状态，CRC余数计算器被配置为顺序地将由第一至第三移位寄存器保持的信息输入到CRC生成方程式以计算通过除法获得的余数，以及CRC确定部分，其输出指示信息是否正确编程了第一至第三个保险丝。

2. 发明申请

US20070226552A1 Semiconductor integrated circuit and the same checking method 失效
标题翻译：半导体集成电路和相同的检查方法
公开(公告)号：US20070226552A1
公开(公告)日：2007-09-27
申请号：US11645509
申请日：2006-12-27
申请人： Natsuki Kushiyama , Shigeaki Iwasa
发明人： Natsuki Kushiyama , Shigeaki Iwasa
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/1004 , G11C11/41 , G11C29/02 , G11C29/027 , G11C2029/4402
摘要： A semiconductor integrated circuit has a cell array, a redundancy cell capable of replacing a defective cell, a redundancy control circuit, a plurality of first fuses programmed in accordance with identification information for specifying a chip mounting the cell array, a plurality of second fuses programmed in accordance with the redundancy information for replacing the defective memory cell with the redundancy cell and various setting information of the chip, a plurality of third fuses programmed in accordance with a CRC code generated based on the redundancy information, various setting information of the chip and the identification information, a first shift register configured to hold states of the plurality of first fuses, a second shift register configured to be connected in cascade to the first shift register and to hold states of the plurality of second fuses, a third shift register configured to be connected to the first and second shift registers in cascade and to hold states of the plurality of third fuses, a CRC remainder calculator configured to sequentially input information held by the first to third shift registers to a CRC generating equation to calculate a remainder obtained by division, and a CRC determination part configured to output information indicative of whether the first to third fuses are correctly programmed.
摘要翻译：半导体集成电路具有单元阵列，能够替代缺陷单元的冗余单元，冗余控制电路，根据用于指定芯片安装单元阵列的识别信息编程的多个第一保险丝，多个第二保险丝编程根据用于用冗余单元替换缺陷存储单元的冗余信息和芯片的各种设置信息，根据基于冗余信息生成的CRC码编程的多个第三保险丝，芯片的各种设置信息和所述识别信息，被配置为保持所述多个第一保险丝的状态的第一移位寄存器，配置为级联连接到所述第一移位寄存器并保持所述多个第二保险丝的状态的第二移位寄存器，配置为被连接到级联的第一和第二移位寄存器并保持状态所述CRC余量计算器被配置为将由所述第一至第三移位寄存器保持的信息顺序地输入到CRC生成方程式，以计算通过除法获得的余数，以及CRC确定部分，被配置为输出指示是否第一至第三个熔丝正确编程。

3. 发明授权

US5522058A Distributed shared-memory multiprocessor system with reduced traffic on shared bus 失效
标题翻译：分布式共享内存多处理器系统，在共享总线上减少流量
公开(公告)号：US5522058A
公开(公告)日：1996-05-28
申请号：US112811
申请日：1993-08-11
申请人： Shigeaki Iwasa , Takashi Omizo
发明人： Shigeaki Iwasa , Takashi Omizo
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/0826 , G06F2212/2542 , G06F2212/622
摘要： A distributed shared-memory multiprocessor system capable of reducing a traffic on the shared bus, without imposing any constraint concerning the types of variables to be accessed in the parallel programs, such that a high system extensibility can be realized. The system is formed by a plurality of processor units coupled through a shared bus, where each processor unit comprises: a CPU; a main memory connected with the CPU through an internal bus, for storing a distributed part of data entries of a shared-memory of the system; a cache memory associated with the CPU and connected with the main memory through the internal bus, for caching selected data entries of the shared-memory; and a sharing management unit connected with the main memory and the cache memory through the internal bus, For interfacing the internal bus and the shared bus according to a sharing state for each data entry of the main memory and a cache state of each data entry of the cache memory.
摘要翻译：一种分布式共享存储器多处理器系统，能够减少共享总线上的流量，而不会对并行程序中要访问的变量的类型施加任何约束，从而可以实现高系统可扩展性。该系统由通过共享总线耦合的多个处理器单元形成，其中每个处理器单元包括：CPU; 通过内部总线与CPU连接的主存储器，用于存储系统的共享存储器的数据条目的分布式部分; 与CPU相关联的高速缓冲存储器，并通过内部总线与主存储器连接，用于缓存共享存储器的选定数据条目; 以及通过内部总线与主存储器和高速缓冲存储器连接的共享管理单元，用于根据主存储器的每个数据条目的共享状态和内部总线和共享总线的每个数据条目的高速缓存状态缓存内存。

4. 发明申请

US20100100684A1 SET ASSOCIATIVE CACHE APPARATUS, SET ASSOCIATIVE CACHE METHOD AND PROCESSOR SYSTEM 审中-公开
标题翻译：设置相关缓存设备，设置相关缓存方法和处理器系统
公开(公告)号：US20100100684A1
公开(公告)日：2010-04-22
申请号：US12580720
申请日：2009-10-16
申请人： Yasuhiko Kurosawa , Atsushi Kameyama , Shigeaki Iwasa , Hiroo Hayashi , Mitsuo Saito
发明人： Yasuhiko Kurosawa , Atsushi Kameyama , Shigeaki Iwasa , Hiroo Hayashi , Mitsuo Saito
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864 , G06F12/0846 , G06F12/0886 , G06F2212/1016
摘要： A set associative cache memory includes a tag memory configured to store tags which are predetermined high-order bits of an address, a tag comparator configured to compare a tag in a request address (RA) with the tag stored in the tag memory and a data memory configured to incorporate way information obtained through a comparison by the tag comparator in part of a column address.
摘要翻译：集合关联高速缓冲存储器包括：标签存储器，被配置为存储地址的预定高位位置的标签;被配置为将请求地址（RA）中的标签与存储在标签存储器中的标签进行比较的标签比较器，以及数据存储器被配置为结合通过标签比较器在列地址中的一部分比较获得的方式信息。

5. 发明申请

US20140082263A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20140082263A1
公开(公告)日：2014-03-20
申请号：US14004788
申请日：2011-09-20
申请人： Shigeaki Iwasa , Kohei Oikawa
发明人： Shigeaki Iwasa , Kohei Oikawa
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0659 , G06F3/0679
摘要： According to one embodiment, a memory system includes a plurality of nonvolatile memories, an address converter, a plurality of channel controllers, and a controller. The plurality of nonvolatile memories is connected to respective channels. The address converter converts a logical address of a read request into a physical address of the nonvolatile memories. Each of the channel controllers is provided to each of the channels. Each of the channel controllers has a plurality of queues, each queues stores at least two read request. The controller selects a queue which stores no read request, and transfers the read request to the selected queue.
摘要翻译：根据一个实施例，存储器系统包括多个非易失性存储器，地址转换器，多个通道控制器和控制器。多个非易失性存储器连接到相应的通道。地址转换器将读请求的逻辑地址转换为非易失性存储器的物理地址。每个通道控制器被提供给每个通道。每个信道控制器具有多个队列，每个队列存储至少两个读请求。控制器选择不存储读取请求的队列，并将读取的请求传送到所选择的队列。

6. 发明授权

US08145804B2 Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor 有权
标题翻译：用于传送数据以维持双端处理器中优选插槽位置的系统和方法
公开(公告)号：US08145804B2
公开(公告)日：2012-03-27
申请号：US12563756
申请日：2009-09-21
申请人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
发明人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
IPC分类号： G06F13/28
CPC分类号： G06F9/30007 , G06F9/3824
摘要： A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
摘要翻译：一种具有多个处理元件的双端式多处理器系统，每个处理单元包括处理器核心，本地存储器和存储器流控制器。存储器流控制器在本地存储器和处理元件外部的数据源之间传送数据。如果处理元件和数据源实现具有相同字节数的数据表示，则每个多字数据行以与数据源中相同的字顺序存储在本地存储器中。如果处理元件和数据源实现具有不同端点的数据表示，则当数据在本地存储器和数据源之间传送时，每个多字数据行的字被转置。处理元件可以包括用于添加双字的电路，其中，根据数据行中的字是否被转置，电路可以交替地将位从第一个字运送到第二个字，反之亦然。

7. 发明授权

US5241641A Hierarchical cache memory apparatus 失效
标题翻译：分层缓存存储器
公开(公告)号：US5241641A
公开(公告)日：1993-08-31
申请号：US501256
申请日：1990-03-28
申请人： Shigeaki Iwasa , Satoru Hashimoto , Shigehiro Asano
发明人： Shigeaki Iwasa , Satoru Hashimoto , Shigehiro Asano
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0897
摘要： A hierarchical cache memory apparatus assembled in a multiprocessor computer system including a plurality of processors and a memory device, includes a plurality of first cache memory devices arranged in correspondence with the plurality of processors and each including a controller including a first status identification section for identifying status of each of a plurality of pieces of address information, a plurality of first connection devices for connecting the plurality of first cache memory devices in units of a predetermined number of devices to constitute a plurality of mini-cluster devices a plurality of second cache memory devices respectively connected to the first connection devices in correspondence with the plurality of mini-cluster devices, having all the addresses of address information of the plurality of first cache memory devices in the mini-cluster devices, and each comprising a controller including a second status identification section for identifying status of each of the plurality of address information, and a memory device connected to the second connection devices and having all the addresses of the plurality of address information of the plurality of second cache memory devices.

8. 发明授权

US08949572B2 Effective address cache memory, processor and effective address caching method 有权
标题翻译：有效的地址缓存内存，处理器和有效的地址缓存方法
公开(公告)号：US08949572B2
公开(公告)日：2015-02-03
申请号：US12580732
申请日：2009-10-16
申请人： Yasuhiko Kurosawa , Shigeaki Iwasa , Seiji Maeda , Nobuhiro Yoshida , Mitsuo Saito , Hiroo Hayashi
发明人： Yasuhiko Kurosawa , Shigeaki Iwasa , Seiji Maeda , Nobuhiro Yoshida , Mitsuo Saito , Hiroo Hayashi
IPC分类号： G06F12/10
CPC分类号： G06F12/1054 , G06F12/0831
摘要： An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
摘要翻译：有效地址高速缓冲存储器包括：TLB有效页存储器，被配置为保留包括处理的有效地址的预定高位的有效页标签的条目数据，并且当有效页标签与有效页标签匹配时输出命中信号从处理器数据存储器，被配置为将高效数据与有效页面标签或页面偏移量保持为高速缓存索引; 以及高速缓存状态存储器，被配置为以与高速缓存索引对应的方式保存存储在数据存储器中的高速缓存数据的高速缓存状态。

9. 发明授权

US08332447B2 Systems and methods for performing fixed-point fractional multiplication operations in a SIMD processor 失效
$Systems and methods for performing fixed-point fractional multiplication operations in a SIMD processor$
标题翻译：用于在SIMD处理器中执行定点分数乘法运算的系统和方法
公开(公告)号：US08332447B2
公开(公告)日：2012-12-11
申请号：US12555298
申请日：2009-09-08
申请人： Shigeaki Iwasa
发明人： Shigeaki Iwasa
IPC分类号： G06F12/14 , G06F12/00
CPC分类号： G06F9/3001 , G06F7/523 , G06F7/5443 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F2207/3828
摘要： Systems and methods for performing multiplication of fixed-point fractional values with the same throughput as addition and subtraction operations, and without loss of accuracy in the result. In one embodiment, a method includes reading data from a pair of source registers that contains multiple single-width multiplicand values. Each multiplicand value in one of the source registers is paired with a corresponding multiplicand value in the other source register. For each pair of multiplicands, a double-width product is generated, then a single-width portion of the product is selected and stored in a target register. The selection of the single-width portion is performed by shifting the double-width products in funnel shifters. The immediate shifting of the double-width products to select the single-width portions allows the operation to achieve the same throughput as addition and subtraction operations.
摘要翻译：用于执行具有与加法运算和减法运算相同的吞吐量的定点分数值相乘的系统和方法，并且不会在结果中失去精度。在一个实施例中，一种方法包括从包含多个单宽度被乘数值的一对源寄存器读取数据。一个源寄存器中的每个被乘数值与另一个源寄存器中的相应乘法器值配对。对于每对被乘数，产生双宽度乘积，则产品的单宽度部分被选择并存储在目标寄存器中。通过移动漏斗移位器中的双宽度产品来进行单宽度部分的选择。双宽度产品立即移动以选择单宽度部分允许操作实现与加法和减法操作相同的吞吐量。

10. 发明申请

US20110072170A1 Systems and Methods for Transferring Data to Maintain Preferred Slot Positions in a Bi-endian Processor 有权
标题翻译：用于传输数据以保持双端处理器中优选插槽位置的系统和方法
公开(公告)号：US20110072170A1
公开(公告)日：2011-03-24
申请号：US12563756
申请日：2009-09-21
申请人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
发明人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
IPC分类号： G06F13/28 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30007 , G06F9/3824
摘要： A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
摘要翻译：一种具有多个处理元件的双端式多处理器系统，每个处理单元包括处理器核心，本地存储器和存储器流控制器。存储器流控制器在本地存储器和处理元件外部的数据源之间传送数据。如果处理元件和数据源实现具有相同字节数的数据表示，则每个多字数据行以与数据源中相同的字顺序存储在本地存储器中。如果处理元件和数据源实现具有不同端点的数据表示，则当数据在本地存储器和数据源之间传送时，每个多字数据行的字被转置。处理元件可以包括用于添加双字的电路，其中，根据数据行中的字是否被转置，电路可以交替地将位从第一个字运送到第二个字，反之亦然。

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