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1. 发明授权

US06385703B1 Speculative request pointer advance for fast back-to-back reads 有权
标题翻译：用于快速背对背读取的推测请求指针
公开(公告)号：US06385703B1
公开(公告)日：2002-05-07
申请号：US09205647
申请日：1998-12-03
申请人： Narendra S. Khandekar , David D. Lent , Zohar Bogin
发明人： Narendra S. Khandekar , David D. Lent , Zohar Bogin
IPC分类号： G06F1314
CPC分类号： G06F12/0831 , G06F2212/507
摘要： A computer system that includes a host processor (HP), a system memory (SM), and a host bridge coupled to the HP and SM is provided. The host bridge asserts a first read request to the SM and, prior to availability of snoop results in connection with the first read request, the host bridge asserts a following second read request to the SM.
摘要翻译：提供了一种包括主机处理器（HP），系统存储器（SM）和耦合到HP和SM的主机桥的计算机系统。主桥向SM发出第一次读取请求，并且在与第一个读取请求相关的侦听结果的可用性之前，主桥向SM发出以下第二个读取请求。

2. 发明授权

US06502150B1 Method and apparatus for resource sharing in a multi-processor system 失效
标题翻译：多处理器系统资源共享的方法和装置
公开(公告)号：US06502150B1
公开(公告)日：2002-12-31
申请号：US09205649
申请日：1998-12-03
申请人： Zohar Bogin , Narendra S. Khandekar , Steve J. Clohset
发明人： Zohar Bogin , Narendra S. Khandekar , Steve J. Clohset
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： A computer system that includes at least two host agents is provided. The computer system further includes a chipset that includes a resource to be shared by the at least two host agents. The chipset is coupled to the-at least two host agents. The chipset prevents a first host agent, that occupies the shared resource to access the shared resource until a second host agent, has made progress in accessing said shared resource.
摘要翻译：提供了包括至少两个主机代理的计算机系统。计算机系统还包括芯片组，其包括要由至少两个主机代理共享的资源。芯片组耦合到至少两个主机代理。芯片组防止占用共享资源的第一主机代理访问共享资源，直到第二个主机代理在访问所述共享资源时取得进展。

3. 发明授权

US6157397A AGP read and CPU wire coherency 失效
标题翻译： AGP读取和CPU线的一致性
公开(公告)号：US6157397A
公开(公告)日：2000-12-05
申请号：US50381
申请日：1998-03-30
申请人： Zohar Bogin , Narendra S. Khandekar , Vincent E. VonBokern
发明人： Zohar Bogin , Narendra S. Khandekar , Vincent E. VonBokern
IPC分类号： G06F3/14 , G06F13/00
CPC分类号： G06F3/14
摘要： A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to read and flushes the data to the storage element prior to the component reading the address associated with the data in the storage element.
摘要翻译：用于图形设备读取和处理器写入一致性的方法从处理器接收写入请求，以将数据写入存储元件，以便组件在组件读取与数据相关联的地址之前将数据读取和刷新到存储元件存储元件

4. 发明授权

US06314497B1 Apparatus and method for maintaining cache coherency in a memory system 有权
标题翻译：用于在存储器系统中维持高速缓存一致性的装置和方法
公开(公告)号：US06314497B1
公开(公告)日：2001-11-06
申请号：US09205646
申请日：1998-12-03
申请人： Steve J. Clohset , Narendra S. Khandekar , Zohar Bogin
发明人： Steve J. Clohset , Narendra S. Khandekar , Zohar Bogin
IPC分类号： G06F1212
CPC分类号： G06F12/0835 , G06F12/0804
摘要： According to one embodiment, a computer system is disclosed. The computer system includes a processor, a memory, an inverting device, a storage device coupled to the inverting device and a device coupled to the storage device. The device receives byte enable information and inverted information and provides inverted byte enable information to the memory upon a write back operation to the memory.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括处理器，存储器，反相装置，耦合到反相装置的存储装置和耦合到存储装置的装置。该设备接收字节使能信息和反相信息，并且在对存储器的回写操作时向存储器提供反转字节使能信息。

5. 发明授权

US06243781B1 Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe 失效
标题翻译：在从出站管道执行发布和未发布的总线事务时，通过将非发布的事务存储在辅助缓冲区中来避免死锁
公开(公告)号：US06243781B1
公开(公告)日：2001-06-05
申请号：US09205051
申请日：1998-12-03
申请人： Wishwesh Gandhi , Tuong Trieu , Ashish Gadagkar , Zohar Bogin , David D. Lent
发明人： Wishwesh Gandhi , Tuong Trieu , Ashish Gadagkar , Zohar Bogin , David D. Lent
IPC分类号： G06F1314
CPC分类号： G06F13/4036
摘要： In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head of the outbound pipe is moved aside and into an auxiliary buffer to avoid a potential blockage of the outbound pipe. The auxiliary buffer is for holding transaction information and return data of the rejected non-posted transaction. The rejected transaction is eventually completed from the auxiliary buffer as determined by an arbiter.
摘要翻译：在具有用于以FIFO方式处理非发布和发布的交易的出站管道的总线资源中，在出站管道的头部处的被拒绝的非贴现事务被移动到辅助缓冲器中，以避免潜在的阻塞出站管道辅助缓冲区用于保存交易信息并返回被拒绝的非贴现交易的数据。被拒绝的事务最终由仲裁器确定的辅助缓冲区完成。

6. 发明授权

US06314472B1 Abort of DRAM read ahead when PCI read multiple has ended 失效
标题翻译：当PCI读取多个已经结束时，DRAM的中止被读取
公开(公告)号：US06314472B1
公开(公告)日：2001-11-06
申请号：US09203127
申请日：1998-12-01
申请人： Tuong P. Trieu , David D. Lent , Ashish S. Gadagkar , Vincent E. VonBokern , Zohar Bogin
发明人： Tuong P. Trieu , David D. Lent , Ashish S. Gadagkar , Vincent E. VonBokern , Zohar Bogin
IPC分类号： G06F300
CPC分类号： G06F13/161
摘要： A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.
摘要翻译：提供计算机系统。计算机系统包括主机处理器（HP），系统存储器（SM）以及输入/输出（I / O）主设备，以执行对SM的连续数据流的读取。计算机系统还包括耦合到HP，SM和I / O主设备的桥。当I / O主设备从SM读取连续的数据流时，桥接器向前读取SM。响应于I / O主设备的脱离接口，桥接器在对SM进行访问提交之前中止对SM的预读访问。

7. 发明授权

US06202112B1 Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge 有权
标题翻译：仲裁方法，以避免跨越桥梁进行交易时的僵局和活锁
公开(公告)号：US06202112B1
公开(公告)日：2001-03-13
申请号：US09205351
申请日：1998-12-03
申请人： Ashish Gadagkar , Zohar Bogin , Narendra Khandekar , David D. Lent
发明人： Ashish Gadagkar , Zohar Bogin , Narendra Khandekar , David D. Lent
IPC分类号： G06F1342
CPC分类号： G06F13/4036
摘要： An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.
摘要翻译：本发明的一个实施例涉及一种具有用于缓冲交易信息和从各种设备传输到总线的数据的出站管的桥。桥接器具有用于授予与这些设备相关联的请求的仲裁器以访问出站管道，用于将事务信息和数据传送到管道中。如果出站管道不可用于接受进一步的交易信息或数据，则桥接器响应于与来自第一设备的初始事务相关联的初始请求生成拒绝信号。桥接器具有用于响应于拒绝信号而产生用于初始事务的重试响应的响应控制逻辑。桥接器能够响应于拒绝信号来声明印记信号。响应于该邮票被断言的仲裁者等待，而不允许任何其他较低优先级的请求访问出站管道，直到来自第一个设备的后续事务进行。

8. 发明授权

US06237055B1 Avoiding livelock when performing a long stream of transactions 失效
标题翻译：执行长时间的事务时避免活动锁定
公开(公告)号：US06237055B1
公开(公告)日：2001-05-22
申请号：US09205024
申请日：1998-12-03
申请人： Tuong Trieu , David D. Lent , Zohar Bogin , Ashish Gadagkar
发明人： Tuong Trieu , David D. Lent , Zohar Bogin , Ashish Gadagkar
IPC分类号： G06F13362
CPC分类号： G06F13/364
摘要： An arbiter comprising logic circuitry configured to delay granting bus ownership to an agent X in response to receiving a first signal which indicates that a device coupled to the bus is not available to service transactions directed at the device over the bus. For instance, the device may be a bridge and the grant is delayed if an inbound pipe of the bridge is full. The arbiter may provide a borrowed grant to an outbound pipe of the device for performing a transaction on the bus while waiting for an inbound pipe of the device to become available.
摘要翻译：一种仲裁器，包括逻辑电路，其被配置为响应于接收到指示耦合到总线的设备不能用于通过总线对设备进行服务的事务的第一信号来延迟向代理X授予总线所有权。例如，如果桥的入站管道已满，则设备可能是桥接器，并且延迟许可。仲裁器可以向设备的出站管道提供借用的授权，用于在等待设备的入站管道变得可用时在总线上进行交易。

9. 发明申请

US20080133952A1 Power saving for isochronous data streams in a computer system 有权
标题翻译：节电计算机系统中的同步数据流
公开(公告)号：US20080133952A1
公开(公告)日：2008-06-05
申请号：US11633183
申请日：2006-12-04
申请人： Chai Huat Gan , Darren Abramson , Zohar Bogin
发明人： Chai Huat Gan , Darren Abramson , Zohar Bogin
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G06F1/3225
摘要： For isochronous data steams processed by a computer system, for example high definition audio streams, embodiments keep track of the free space available in the input and output buffers for the data streams. The available free space in the buffers determines whether various low power entry and exit thresholds are met or not. If all low power entry thresholds are met, then various circuits such as clocks, phase locked loops, and direct media interface links, may be put into a low power state, and the data stream controller enters an idle window so that memory requests are not serviced. During this time, system DRAM may begin refresh. Once the low power state has been entered into, if any exit threshold is met, then the low power state is ended. Other embodiments are described and claimed.
摘要翻译：对于由计算机系统处理的等时数据流，例如高清晰度音频流，实施例跟踪用于数据流的输入和输出缓冲器中的可用空间。缓冲器中的可用空间确定是否满足各种低功率进入和退出阈值。如果满足所有低功率入口阈值，则诸如时钟，锁相环和直接介质接口链路的各种电路可能被置于低功率状态，并且数据流控制器进入空闲窗口，使得存储器请求不是服务。在此期间，系统DRAM可能会开始刷新。一旦输入低功率状态，如果满足任何退出阈值，则低功率状态结束。描述和要求保护其他实施例。

10. 发明授权

US07181605B2 Deterministic shut down of memory devices in response to a system warm reset 有权
标题翻译：响应于系统热复位，确定性地关闭存储器件
公开(公告)号：US07181605B2
公开(公告)日：2007-02-20
申请号：US10693226
申请日：2003-10-24
申请人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
发明人： Zohar Bogin , Surya Kareenahalli , Anoop Mukker , David Sastry , Tuong Trieu
IPC分类号： G06F9/00
CPC分类号： G06F1/24
摘要： A method to deterministically shut down memory devices in response to a system warm reset has been disclosed. One embodiment of the method includes causing a first type of reset in a number of memory devices in a system in response to a second type of reset in the system being initiated if the memory devices are not initialized and enabling a deterministic shutdown mode in a memory controller, which is coupled to the memory devices, after the memory devices have been initialized. Other embodiments are described and claimed.
摘要翻译：已经公开了响应于系统热复位来确定地关闭存储器件的方法。该方法的一个实施例包括在系统中响应于系统中的第二类型的复位而引起系统中的多个存储器件中的第一类型的复位，如果存储器件未被初始化并且使能存储器中的确定性关断模式控制器，其在存储器件初始化之后耦合到存储器件。描述和要求保护其他实施例。

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