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1. 发明授权

US06215702B1 Method of maintaining constant erasing speeds for non-volatile memory cells 有权
标题翻译：保持非易失性存储单元的不断擦除速度的方法
公开(公告)号：US06215702B1
公开(公告)日：2001-04-10
申请号：US09504696
申请日：2000-02-16
申请人： Narbeh Derhacobian , Shane C. Hollmer , Ravi S. Sunkavalli
发明人： Narbeh Derhacobian , Shane C. Hollmer , Ravi S. Sunkavalli
IPC分类号： G11C1134
CPC分类号： H01L29/7923 , G11C11/5671 , G11C16/0475 , G11C16/14
摘要： A method of erasing a memory cell that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a first cycle of voltages across the gate and the first region so that the first amount of charge is removed from the charge trapping region. A second amount of charge is written into the charge trapping region and subsequently a second cycle of one or more voltages is applied across the gate and the first region so that the second amount of charge is removed from the charge trapping region, wherein the initial applied voltage of the second cycle of voltages is equal to the final applied voltage of the first cycle of voltages.
摘要翻译：一种擦除具有第一区域和第二区域以及沟道上方的栅极的存储单元的方法，以及包含初始电荷量的电荷捕获区域。该方法包括跨越栅极和第一区域施加电压的第一周期，使得从电荷俘获区域去除第一电荷量。第二量的电荷被写入电荷俘获区域中，随后在栅极和第一区域两端施加一个或多个电压的第二周期，使得从电荷俘获区域去除第二电荷量，其中初始施加电压的第二周期的电压等于第一周期电压的最终施加电压。

2. 发明授权

US06970386B2 Method and apparatus for detecting exposure of a semiconductor circuit to ultra-violet light 有权
标题翻译：用于检测半导体电路对紫外光的曝光的方法和装置
公开(公告)号：US06970386B2
公开(公告)日：2005-11-29
申请号：US10378414
申请日：2003-03-03
申请人： Shane C. Hollmer
发明人： Shane C. Hollmer
IPC分类号： G11C16/18 , G11C16/22 , G11C16/04
CPC分类号： G11C16/18 , G11C16/22
摘要： A method and apparatus are disclosed for detecting if a semiconductor circuit has been exposed to ultra-violet light. An ultra-violet light detection circuit detects exposure to ultra-violet light and will automatically activate a security violation signal. The security violation signal may optionally initiate a routine to clear sensitive data from memory or prevent the semiconductor circuit from further operation. The ultra-violet light detection circuit detects whether a semiconductor circuit has been exposed to ultra-violet light, for example, by employing a dedicated mini-array of non-volatile memory cells. At least two active bit lines, blprg and bler, are employed corresponding to program and erase, respectively. One of the bit lines is only programmable and the other bit line is only eraseable. Generally, all of the bits in the dedicated non-volatile memory array are initially in approximately the same state, which could be erased, programmed or somewhere in between. An offset current is added to one bit line and a change in the resulting current difference is used to detect an exposure to ultra-violet light.
摘要翻译：公开了一种用于检测半导体电路是否已经暴露于紫外光的方法和装置。紫外光检测电路检测到紫外光的曝光，并自动激活安全违规信号。安全违规信号可以可选地启动例程以从存储器清除敏感数据或防止半导体电路进一步操作。紫外光检测电路例如通过采用非易失性存储单元的专用微型阵列来检测半导体电路是否已经暴露于紫外光。对应于编程和擦除分别使用至少两个有效位线blprg和bler。其中一个位线只能编程，另一个位线只能擦除。通常，专用非易失性存储器阵列中的所有位最初处于大致相同的状态，这可能被擦除，编程或其间的某处。偏移电流被添加到一个位线，并且所得到的电流差的变化用于检测对紫外光的曝光。

3. 发明授权

US06545912B1 Erase verify mode to evaluate negative Vt's 有权
标题翻译：擦除验证模式来评估负Vt
公开(公告)号：US06545912B1
公开(公告)日：2003-04-08
申请号：US09727656
申请日：2000-11-30
申请人： Joseph G. Pawletko , Shane C. Hollmer , Pau-Ling Chen
发明人： Joseph G. Pawletko , Shane C. Hollmer , Pau-Ling Chen
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C16/344 , G11C29/50
摘要： A method is provided to determine erase threshold voltages of memory transistors and thereby identify unusable memory transistors. A voltage is applied to the common source of a selected memory transistor and gradually incremented until a logical HIGH bit is read as a logical LOW bit. By iteratively incrementing Vbias, the erase threshold voltage for each memory transistor can be determined. In one process, the erase threshold voltage for each memory transistor in a memory device is determined and then the memory device is put under stress tests to simulate normal operative conditions. After the stress tests, the erase threshold voltage of each memory transistor can be once again determined to ascertain the change in the erase threshold voltage, i.e., the data retention characteristic, of each memory transistor.
摘要翻译：提供了一种方法来确定存储晶体管的擦除阈值电压，从而识别不可用的存储晶体管。电压被施加到所选择的存储晶体管的公共源，并逐渐增加，直到逻辑高位被读为逻辑低位。通过迭代地增加Vbias，可以确定每个存储晶体管的擦除阈值电压。在一个过程中，确定存储器件中每个存储晶体管的擦除阈值电压，然后将存储器件置于压力测试中以模拟正常工作状态。在应力测试之后，可以再次确定每个存储晶体管的擦除阈值电压，以确定每个存储晶体管的擦除阈值电压（即数据保持特性）的变化。

4. 发明授权

US06477083B1 Select transistor architecture for a virtual ground non-volatile memory cell array 失效
标题翻译：选择用于虚拟地面非易失性存储单元阵列的晶体管架构
公开(公告)号：US06477083B1
公开(公告)日：2002-11-05
申请号：US09686685
申请日：2000-10-11
申请人： Richard M. Fastow , Mark W. Randolph , Shane C. Hollmer
发明人： Richard M. Fastow , Mark W. Randolph , Shane C. Hollmer
IPC分类号： G11C1604
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , G11C16/14 , H01L27/115
摘要： A bit line selector for a virtual ground non-volatile read only memory (“NROM”) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to the bit line and the channel width is parallel to the bit line. Subsequent reduction in the bit line pitch does not affect the channel width of the select transistors or their drive current.
摘要翻译：公开了用于虚拟非易失性只读存储器（“NROM”）单元阵列的位线选择器。选择器晶体管被定向成使得沟道长度垂直于位线并且沟道宽度平行于位线。位线间距的随后减小不会影响选择晶体管的沟道宽度或其驱动电流。

5. 发明授权

US06185130B2 Programmable current source 有权
标题翻译：可编程电流源
公开(公告)号：US06185130B2
公开(公告)日：2001-02-06
申请号：US09420209
申请日：1999-10-18
申请人： Shane C. Hollmer , Joseph G. Pawletko
发明人： Shane C. Hollmer , Joseph G. Pawletko
IPC分类号： G11C1606
CPC分类号： G11C16/24 , G11C5/147 , G11C16/3436 , G11C29/12
摘要： A programmable reference current source used with a memory array during test and user modes to program or erase verify. The reference current source is programmable so that optimal reference currents can be determined during test mode. A value representing the optimal reference current is stored so that the reference current source provides the determined reference current during user mode.
摘要翻译：在测试期间与存储器阵列一起使用的可编程参考电流源，并且用户模式编程或擦除验证。参考电流源可编程，以便在测试模式下可以确定最佳的参考电流。存储表示最佳参考电流的值，使得参考电流源在用户模式期间提供确定的参考电流。

6. 发明授权

US06418054B1 Embedded methodology to program/erase reference cells used in sensing flash cells 有权
标题翻译：用于编程/擦除用于感测闪存单元的参考单元的嵌入式方法
公开(公告)号：US06418054B1
公开(公告)日：2002-07-09
申请号：US09387421
申请日：1999-08-31
申请人： Shane C. Hollmer
发明人： Shane C. Hollmer
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C16/10 , G11C16/3454
摘要： Programming lines are attached to reference cells of a memory device. A state machine controls voltages and/or currents applied to the reference cells via the programming lines to program and verify a program state of the reference cells. The state machine utilizes existing array cell programming operations conducted by the programming lines to the reference cells. The utilization of internal circuitry of the memory device in the programming of reference cells reduces the sort and test time of the memory device. The memory device may be a flash memory device or any device having reference cells, and the reference cells may be of any configuration or structure, including nitride layer cells.
摘要翻译：编程线连接到存储器件的参考单元。状态机通过编程线控制施加到参考单元的电压和/或电流，以对参考单元的编程状态进行编程和验证。状态机利用编程线对参考单元进行的现有阵列单元编程操作。在参考单元的编程中利用存储器件的内部电路减少了存储器件的分类和测试时间。存储器件可以是闪存器件或具有参考单元的任何器件，并且参考单元可以是包括氮化物层单元的任何配置或结构。

7. 发明授权

US06269025B1 Memory system having a program and erase voltage modifier 有权
标题翻译：具有编程和擦除电压调节器的存储器系统
公开(公告)号：US06269025B1
公开(公告)日：2001-07-31
申请号：US09500699
申请日：2000-02-09
申请人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
发明人： Shane C. Hollmer , Binh Quang Le , Pau-Ling Chen
IPC分类号： G11C1604
CPC分类号： G11C5/147 , G11C16/12 , G11C16/16
摘要： A memory system has the capability to adjust a program or erase voltage if the time to program or erase is excessive. The memory system comprises at least a memory cell, a voltage value storage device, a voltage source, and a voltage adjustment circuit. The voltage value storage device stores a voltage value. The voltage source receives and converts the voltage value into a voltage. The voltage source applies the voltage to at least one memory cell. The voltage adjustment circuit is also coupled to receive the stored voltage value. The voltage adjustment circuit determines the time required to program or erase at least one memory cell using the voltage value. If the time to program or erase at least one memory cell is excessive, the voltage adjustment circuit increments the voltage value stored in the voltage value storage device.
摘要翻译：如果编程或擦除时间过长，存储系统可以调整程序或擦除电压。存储器系统至少包括存储器单元，电压值存储器件，电压源和电压调节电路。电压值存储装置存储电压值。电压源接收并将电压值转换为电压。电压源将电压施加到至少一个存储单元。电压调节电路也耦合以接收存储的电压值。电压调节电路使用电压值来确定编程或擦除至少一个存储单元所需的时间。如果编程或擦除至少一个存储单元的时间过长，则电压调节电路增加存储在电压值存储装置中的电压值。

8. 发明授权

US5978266A Array VSS biasing for NAND array programming reliability 失效
标题翻译：阵列VSS偏置用于NAND阵列编程的可靠性
公开(公告)号：US5978266A
公开(公告)日：1999-11-02
申请号：US24880
申请日：1998-02-17
申请人： Pau-ling Chen , Shane C. Hollmer , Binh Q. Le , Michael S. Chung
发明人： Pau-ling Chen , Shane C. Hollmer , Binh Q. Le , Michael S. Chung
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/10
摘要： A method is provided for biasing a NAND array EEPROM during programming to allow the array to be scaled down further before reach punchthrough. The sources of the ground-select transistors of the NAND array are biased at V.sub.cc instead of ground to reduce the voltage drop across the source and drain of the ground-select transistors. As a result, the channel length of the ground-select transistors can be further shortened before punchthrough is obtained, resulting in a higher density EEPROM.
摘要翻译：提供了一种用于在编程期间偏置NAND阵列EEPROM以允许阵列在进入穿透之前被进一步缩小的方法。 NAND阵列的接地选择晶体管的源极被偏置为Vcc而不是接地，以减小接地选择晶体管的源极和漏极两端的电压降。结果，在获得穿通之前，可以进一步缩短接地选择晶体管的沟道长度，从而产生更高密度的EEPROM。

9. 发明授权

US5579261A Reduced column leakage during programming for a flash memory array 失效
标题翻译：在闪存阵列编程期间降低色谱柱泄漏
公开(公告)号：US5579261A
公开(公告)日：1996-11-26
申请号：US426716
申请日：1995-04-21
申请人： Nader Radjy , Lee E. Cleveland , Jian Chen , Shane C. Hollmer
发明人： Nader Radjy , Lee E. Cleveland , Jian Chen , Shane C. Hollmer
IPC分类号： G11C16/26 , G11C16/34 , G11C16/02
CPC分类号： G11C16/3409 , G11C16/26 , G11C16/3404
摘要： A method for programing a cell in an array of flash memory cells connected to a bit line using hot-electron injection. In the method, a negative word line voltage is applied to unselected cells connected to the bit line to create a negative gate to source voltage in the unselected cells. The negative gate to source voltage in the unselected cells is provided to prevent overerased cells, or cells which have a negative threshold, from turning on to reduce bit line leakage current.
摘要翻译：一种用于使用热电子注入来连接到位线的闪存单元的阵列中的单元的编程方法。在该方法中，将负字线电压施加到连接到位线的未选择的单元，以在未选择的单元中产生负栅极至源极电压。提供未选择的单元中的负栅极到源极电压以防止过电压的单元或具有负阈值的单元导通以减少位线泄漏电流。

10. 发明授权

US06181605B2 Global erase/program verification apparatus and method 有权
标题翻译：全局擦除/程序验证装置和方法
公开(公告)号：US06181605B2
公开(公告)日：2001-01-30
申请号：US09414750
申请日：1999-10-06
申请人： Shane C. Hollmer , Joseph G. Pawletko , Michael S. C. Chung
发明人： Shane C. Hollmer , Joseph G. Pawletko , Michael S. C. Chung
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/3436 , G11C16/3459
摘要： A technique to determine whether multiple memory cells are programmed or erased. After a program or erase operation, respective program or erase verify operations are performed. A logical gate is coupled to measure the state of each memory cell. When all memory cells selected to be programmed or erased are programmed or erased then the output of the logical gate indicates successful program or erase verify. Thus, by using a single logical gate coupled to measure the states of multiple memory cells, only the output of the logical gate need be measured to determine successful program or erase verification of multiple memory cells.
摘要翻译：确定多个存储器单元是否被编程或擦除的技术。在编程或擦除操作之后，执行相应的编程或擦除验证操作。耦合逻辑门来测量每个存储单元的状态。当所有被选择被编程或擦除的存储单元被编程或擦除时，逻辑门的输出指示成功的程序或擦除验证。因此，通过使用耦合以测量多个存储器单元的状态的单个逻辑门，仅需要测量逻辑门的输出以确定多个存储单元的成功编程或擦除验证。

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