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1. 发明授权

US06418067B1 Semiconductor memory device suitable for merging with logic 失效
标题翻译：半导体存储器件适用于与逻辑电路合并
公开(公告)号：US06418067B1
公开(公告)日：2002-07-09
申请号：US09592454
申请日：2000-06-09
申请人： Naoya Watanabe , Akira Yamazaki , Kazutami Arimoto , Takeshi Fujino , Isamu Hayashi , Hideyuki Noda
发明人： Naoya Watanabe , Akira Yamazaki , Kazutami Arimoto , Takeshi Fujino , Isamu Hayashi , Hideyuki Noda
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C11/4076 , G11C29/846
摘要： Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.
摘要翻译：读取数据线对，写入数据线对，备用读取数据线对和备用写入数据线对，提供在存储单元阵列上的列方向上延伸。通过替换数据线对执行备用位修复。列冗余控制电路改变用于输出数据写入模式和数据读取模式的备用确定结果的定时。提供一种适于与逻辑并入并能够降低电流消耗并实现更高操作频率的半导体存储器件。

2. 发明授权

US07102954B2 Semiconductor integrated circuit device having logic circuit and dynamic random access memory on the same chip 有权
标题翻译：具有在同一芯片上的逻辑电路和动态随机存取存储器的半导体集成电路器件
公开(公告)号：US07102954B2
公开(公告)日：2006-09-05
申请号：US10714393
申请日：2003-11-17
申请人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
发明人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
IPC分类号： G11C5/14 , G11C29/06
CPC分类号： H01L27/10897 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C29/12
摘要： In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
摘要翻译：在存储器电路中，以与逻辑晶体管相同的工艺形成的晶体管用于外围电路，除了要被提供高电压的区域之外。因此，可以简化制造过程，并且提供以高速运行的逻辑合并存储器。

3. 发明授权

US06649984B1 Logic-merged memory 有权
标题翻译：逻辑合并记忆
公开(公告)号：US06649984B1
公开(公告)日：2003-11-18
申请号：US09632333
申请日：2000-08-03
申请人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
发明人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Takeshi Fujino
IPC分类号： H01L29792
CPC分类号： H01L27/10897 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C29/12
摘要： In a memory circuit, a transistor formed in the same process as that of a logic transistor is used for peripheral circuitry except for a region to be supplied with high voltage. Thus, the manufacturing process can be simplified and a logic-merged memory operating at a high speed is provided.
摘要翻译：在存储器电路中，以与逻辑晶体管相同的工艺形成的晶体管用于外围电路，除了要被提供高电压的区域之外。因此，可以简化制造过程，并且提供以高速运行的逻辑合并存储器。

4. 发明授权

US06507532B1 Semiconductor memory device having row-related circuit operating at high speed 失效
标题翻译：具有行相关电路的半导体存储器件以高速工作
公开(公告)号：US06507532B1
公开(公告)日：2003-01-14
申请号：US09722687
申请日：2000-11-28
申请人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
发明人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/18 , G11C11/4087
摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.
摘要翻译：中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号时钟周期，用于传输到每个存储器子块。备用确定电路与时钟信号异步地执行备用确定。可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

5. 发明授权

US06590511B2 Retrievable memory capable of outputting a piece of data with respect to a plurality of results of retrieve 失效
公开(公告)号：US06590511B2
公开(公告)日：2003-07-08
申请号：US09775711
申请日：2001-02-05
申请人： Isamu Hayashi , Takeshi Fujino , Hideyuki Noda , Hiroki Shimano
发明人： Isamu Hayashi , Takeshi Fujino , Hideyuki Noda , Hiroki Shimano
IPC分类号： H03M700
CPC分类号： H03M7/3084 , G11C15/00 , G11C15/04
摘要： A retrievable memory is provided with a priority encoder. The priority encoder is constituted by encoder units. Each of the encoder units is constituted by an inverter, N-channel MOS transistors and an AND gate. Upon receipt of a signal of H level from a matching line, the encoder unit outputs a signal of H level to a word line, and also outputs a signal of L level to a matching line active signal line MLA1. Then, the encoder units respectively output signals of L level to the word lines. Consequently, even when a plurality of results of a retrieving process are obtained, it is possible to output single data.

6. 发明授权

US07139208B2 Refresh-free dynamic semiconductor memory device 失效
公开(公告)号：US07139208B2
公开(公告)日：2006-11-21
申请号：US11165273
申请日：2005-06-24
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C7/20 , G11C5/14
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.

7. 发明授权

US06272034B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06272034B1
公开(公告)日：2001-08-07
申请号：US09606402
申请日：2000-06-29
申请人： Mitsuya Kinoshita , Fukashi Morishita , Kazutami Arimoto , Takeshi Fujino , Tetsushi Tanizaki , Takahiro Tsuruda , Teruhiko Amano , Mako Kobayashi
发明人： Mitsuya Kinoshita , Fukashi Morishita , Kazutami Arimoto , Takeshi Fujino , Tetsushi Tanizaki , Takahiro Tsuruda , Teruhiko Amano , Mako Kobayashi
IPC分类号： G11C502
CPC分类号： G11C5/025
摘要： A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.
摘要翻译：控制存储器单元的操作的控制电路部分集中在中心部分，并且热辐射板通过粘合剂放置在其上。具有MPU等的功能的半导体集成电路经由凸块电极放置在控制电路部分上方。控制电路部分和存储块分别形成在分开的芯片上。

8. 发明授权

US6151244A Dynamic semiconductor memory device 失效
标题翻译：动态半导体存储器件
公开(公告)号：US6151244A
公开(公告)日：2000-11-21
申请号：US176029
申请日：1998-10-21
申请人： Takeshi Fujino , Kazutami Arimoto
发明人： Takeshi Fujino , Kazutami Arimoto
IPC分类号： H01L21/8247 , G11C11/401 , G11C11/4074 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/24
CPC分类号： G11C11/401 , G11C11/4074
摘要： Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.
摘要翻译：由多位一晶体管/一电容型存储单元形成的存储单元最小单元（MCU）沿列方向重复排列，并且位线接触（BCT）相对于行方向在列方向上偏移。位线接点以规定数量的位线为单位重复移位。通过控制每组位线的单元板线和位线的电压，可以获得读取存储单元数据的读取位线和提供参考电位的参考位线的集合。因此，可以减小存储器单元占用面积，并且折叠位线布置中的感测操作是可能的。因此，可以显着减少每一位的存储单元占用面积，并且可以执行折叠位线布置中的感测操作。

9. 发明授权

US06925022B2 Refresh-free dynamic semiconductor memory device 失效
标题翻译：无刷新动态半导体存储器件
公开(公告)号：US06925022B2
公开(公告)日：2005-08-02
申请号：US10229035
申请日：2002-08-28
申请人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
发明人： Kazutami Arimoto , Hiroki Shimano , Takeshi Fujino , Takeshi Hashizume
IPC分类号： G11C11/407 , G11C7/10 , G11C11/401 , G11C11/403 , G11C11/405 , G11C11/406 , G11C11/408 , G11C11/409 , G11C29/02 , G11C29/04 , G11C29/14 , G11C7/20
CPC分类号： G11C29/006 , G11C7/1045 , G11C11/401 , G11C11/406 , G11C11/4087 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C29/50016 , G11C29/83 , G11C2029/1204 , G11C2207/104 , G11C2211/4013 , G11C2211/5641
摘要： In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultaneously driven into a selected state, and storage data of memory cells are read out on both of bit lines in a pair, to perform a sense operation. Thus, the read-out voltage can be increased to improve the data retention characteristics for lengthening a refresh interval, resulting in a reduced power consumption in the data holding mode.
摘要翻译：在数据保持模式下，在正常操作模式下的一位/一个单元方案中的数据存储以双位模式重新排列成数据存储，其中数据以一位/双位单元方式存储。在双电池模式中，两个子字线同时被驱动到选择状态，并且在一对位线上读出存储器单元的存储数据，以执行感测操作。因此，可以增加读出电压以改善用于延长刷新间隔的数据保持特性，导致数据保持模式中的功耗降低。

10. 发明申请

US20050041514A1 Low-power consumption semiconductor memory device 失效
标题翻译：低功耗半导体存储器件
公开(公告)号：US20050041514A1
公开(公告)日：2005-02-24
申请号：US10949365
申请日：2004-09-27
申请人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
发明人： Takeshi Fujino , Kazutami Arimoto , Hiroki Shimano
IPC分类号： G11C11/405 , G11C7/12 , G11C11/409 , G11C11/4094 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C5/00
CPC分类号： G11C11/4094 , G11C7/12
摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.
摘要翻译：存储单元单元包括用于彼此存储互补数据的第一存储元件和第二存储元件。在选择状态下，第一和第二存储元件分别连接到互补位线。在待机状态下，位线被预充电到对应于存储在存储单元单元中的数据的电压（Vcc或GND）。可以实现即使在低电源电压下稳定运行的无刷新，低电流消耗的半导体存储器件。

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