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1. 发明授权

US06272034B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06272034B1
公开(公告)日：2001-08-07
申请号：US09606402
申请日：2000-06-29
申请人： Mitsuya Kinoshita , Fukashi Morishita , Kazutami Arimoto , Takeshi Fujino , Tetsushi Tanizaki , Takahiro Tsuruda , Teruhiko Amano , Mako Kobayashi
发明人： Mitsuya Kinoshita , Fukashi Morishita , Kazutami Arimoto , Takeshi Fujino , Tetsushi Tanizaki , Takahiro Tsuruda , Teruhiko Amano , Mako Kobayashi
IPC分类号： G11C502
CPC分类号： G11C5/025
摘要： A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.
摘要翻译：控制存储器单元的操作的控制电路部分集中在中心部分，并且热辐射板通过粘合剂放置在其上。具有MPU等的功能的半导体集成电路经由凸块电极放置在控制电路部分上方。控制电路部分和存储块分别形成在分开的芯片上。

2. 发明授权

US5914907A Semiconductor memory device capable of increasing chip yields while maintaining rapid operation 失效
标题翻译：半导体存储器件能够在保持快速操作的同时提高芯片产量
公开(公告)号：US5914907A
公开(公告)日：1999-06-22
申请号：US122760
申请日：1998-07-27
申请人： Mako Kobayashi , Tetsushi Tanizaki , Kazutami Arimoto , Teruhiko Amano , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Mitsuya Kinoshita
发明人： Mako Kobayashi , Tetsushi Tanizaki , Kazutami Arimoto , Teruhiko Amano , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Mitsuya Kinoshita
IPC分类号： G11C29/04 , G11C29/00 , G11C29/42 , G11C8/00 , G11C7/00
CPC分类号： G11C29/80 , G11C29/84
摘要： Regular memory cell arrays are arranged in divided regions in three rows and three columns except for the region located at the second row and the second column. The region located at the intersection of the second row and the second column is provided with a redundant memory cell array. The replacement operation of the regular memory cell arrays with the redundant memory cell array is provided for each memory cell block.
摘要翻译：常规存储单元阵列被布置在除了位于第二行和第二列的区域之外的三行和三列的分割区域中。位于第二行和第二列的交叉点的区域设置有冗余存储单元阵列。为每个存储单元块提供具有冗余存储单元阵列的常规存储单元阵列的替换操作。

3. 发明授权

US06337506B2 Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area 失效
标题翻译：半导体存储器件能够在防止芯片面积增加的同时对噪声进行稳定的操作
公开(公告)号：US06337506B2
公开(公告)日：2002-01-08
申请号：US09116887
申请日：1998-07-16
申请人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
发明人： Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Takahiro Tsuruda , Mitsuya Kinoshita , Mako Kobayashi
IPC分类号： H01L2900
CPC分类号： H01L23/552 , G11C5/14 , H01L21/761 , H01L23/585 , H01L27/0203 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A power supply circuit and an oscillation circuit or the like of noise generation sources are concentrated, and the periphery thereof is surrounded by a guard ring. Guard ring is provided to have bonding pads at least partially thereon. Guard ring is effectively provided utilizing the region below bonding pads, so that effective noise reduction is achieved while preventing increase in chip area.
摘要翻译：噪声产生源的电源电路和振荡电路等被集中，其周边被保护环包围。提供保护环以至少部分地具有接合焊盘。利用焊盘下方的区域有效地提供保护环，从而在防止芯片面积的增加的同时实现有效的降噪。

4. 发明授权

US06215720B1 High speed operable semiconductor memory device with memory blocks arranged about the center 失效
标题翻译：具有围绕中心布置的存储块的高速可操作半导体存储器件
公开(公告)号：US06215720B1
公开(公告)日：2001-04-10
申请号：US09478528
申请日：2000-01-06
申请人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
发明人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
IPC分类号： G11C800
CPC分类号： G11C7/222 , G11C5/025 , G11C7/22 , G11C8/12
摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
摘要翻译：主控制电路通过四个本地控制电路提供对对应存储器块的访问。存储块被布置成围绕主控制电路和本地控制电路。控制信号到每个存储器块的延迟量被设置为基本上等于抑制控制信号中的偏斜。可以实现高速DRAM。

5. 发明授权

US6072743A High speed operable semiconductor memory device with memory blocks arranged about the center 失效
标题翻译：具有围绕中心布置的存储块的高速可操作半导体存储器件
公开(公告)号：US6072743A
公开(公告)日：2000-06-06
申请号：US110688
申请日：1998-07-07
申请人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
发明人： Teruhiko Amano , Takahiro Tsuruda , Kazutami Arimoto , Tetsushi Tanizaki , Takeshi Fujino , Mitsuya Kinoshita , Fukashi Morishita , Mako Kobayashi
IPC分类号： G11C5/02 , G11C7/22 , G11C8/12 , G11C8/00
CPC分类号： G11C7/222 , G11C5/025 , G11C7/22 , G11C8/12
摘要： A master control circuit provides access to a corresponding memory block via four local control circuits. The memory blocks are arranged so as to surround the master control circuit and the local control circuits. The amount of delay of a control signal to each memory block is set substantially equal to suppress skew in the control signal. A DRAM of high speed can be realized.
摘要翻译：主控制电路通过四个本地控制电路提供对对应存储器块的访问。存储块被布置成围绕主控制电路和本地控制电路。将控制信号到每个存储块的延迟量设置为基本上等于抑制控制信号中的偏移。可以实现高速DRAM。

6. 发明授权

US6064621A Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement 失效
标题翻译：具有改进的存储器阵列和电源配置的多存储体时钟同步型半导体存储器件
公开(公告)号：US6064621A
公开(公告)日：2000-05-16
申请号：US113147
申请日：1998-07-10
申请人： Tetsushi Tanizaki , Mitsuya Kinoshita , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Mako Kobayashi
发明人： Tetsushi Tanizaki , Mitsuya Kinoshita , Takeshi Fujino , Takahiro Tsuruda , Fukashi Morishita , Teruhiko Amano , Kazutami Arimoto , Mako Kobayashi
IPC分类号： G11C11/41 , G11C5/02 , G11C5/14 , G11C8/00 , G11C8/12 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C5/14 , G11C8/12
摘要： A rectangular semiconductor substrate region is divided into regions arranged in a plurality of rows and columns, and memory array blocks are provided to surround a central region. The plurality of memory array blocks are divided into a plurality of banks. Peripheral regions on both sides of the rectangular semiconductor substrate region are used as regions for providing sense amplifier power supply circuits, and circuits for generating a voltage to be transmitted onto word lines are provided at the four corner regions of the central region. Thus, a large storage capacity semiconductor memory device operating stably at a high speed and with reduced power consumption can be implemented.
摘要翻译：矩形半导体衬底区域被分成多个行和列布置的区域，并且存储器阵列块被设置为围绕中心区域。多个存储器阵列块被分成多个存储体。矩形半导体衬底区域的两侧的周边区域被用作提供感测放大器电源电路的区域，并且在中心区域的四个角区域处设置用于产生要传输到字线上的电压的电路。因此，可以实现以高速和低功耗稳定运行的大容量半导体存储器件。

7. 发明授权

US5909046A Semiconductor integrated circuit device having stable input protection circuit 失效
标题翻译：半导体集成电路器件具有稳定的输入保护电路
公开(公告)号：US5909046A
公开(公告)日：1999-06-01
申请号：US965618
申请日：1997-11-06
申请人： Tetsushi Tanizaki , Fukashi Morishita , Masaki Tsukude , Kazutami Arimoto
发明人： Tetsushi Tanizaki , Fukashi Morishita , Masaki Tsukude , Kazutami Arimoto
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H01L23/62
CPC分类号： H01L27/0248 , H01L24/05 , H01L2924/14
摘要： A conductor line is placed at a layer overlying an input protection circuit electrically coupled to a pad such that the conductor line covers at least a part of the input protection circuit. The conductor line having a sufficiently large width disperses and absorbs the heat generated from the input protection circuit. Since the input protection circuit and the conductor line have a region overlapping with each other in the layout of plan view, an area for layout of the input protection circuit on a chip can be reduced effectively, and prevention of a destruction of the protection circuit due to the heat as well as an improvement of a resistance to the surge can be obtained.
摘要翻译：导体线被放置在覆盖输入保护电路的层上，该输入保护电路电耦合到焊盘，使得导线覆盖输入保护电路的至少一部分。具有足够大的宽度的导体线分散并吸收从输入保护电路产生的热量。由于输入保护电路和导体线在平面图的布局中具有彼此重叠的区域，因此可以有效地降低芯片上的输入保护电路布局的区域，并防止保护电路的破坏可以获得耐热性，并且可以获得耐喘振性的改善。

8. 发明授权

US07007215B2 Test circuit capable of testing embedded memory with reliability 失效
公开(公告)号：US07007215B2
公开(公告)日：2006-02-28
申请号：US10173266
申请日：2002-06-18
申请人： Mitsuya Kinoshita , Tetsushi Tanizaki , Masaru Haraguchi , Katsumi Dosaka
发明人： Mitsuya Kinoshita , Tetsushi Tanizaki , Masaru Haraguchi , Katsumi Dosaka
IPC分类号： G01R31/30
CPC分类号： G11C29/56012 , G01R31/318572 , G01R31/31858 , G11C29/56
摘要： A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.

9. 发明授权

US07032141B2 Semiconductor device including test-facilitating circuit using built-in self test circuit 有权
标题翻译：半导体器件包括使用内置自检电路的测试便利电路
公开(公告)号：US07032141B2
公开(公告)日：2006-04-18
申请号：US10198106
申请日：2002-07-19
申请人： Tetsushi Tanizaki
发明人： Tetsushi Tanizaki
IPC分类号： G11C29/00
CPC分类号： G11C29/20 , G11C29/14
摘要： A test interface circuit, which has a simple pattern generator mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three bits received from a tester, outputs an analysis result to a memory core and controls an operation of the memory core, and an address counter which counts addresses and outputs the addresses to the memory core in accordance with a counter control instruction of two bits received from the tester. It is, therefore, possible to make a circuit for testing the memory core small in scale and to decrease the number of pins for testing the memory core, so that it is possible to use an inexpensive tester and to reduce cost required to test the memory core.
摘要翻译：具有安装在具有安装存储器的半导体器件上的简单图形发生器的测试接口电路由分析从测试器接收的三位指令的命令分析部分组成，将分析结果输出到存储器核心并控制存储器核心的操作，以及根据从测试器接收的两个位的计数器控制指令对地址进行计数并将地址输出到存储器核心的地址计数器。因此，可以制造用于小规模测试存储器芯片的电路并且减少用于测试存储器核心的引脚数量，使得可以使用廉价的测试器并且降低测试存储器所需的成本核心。

10. 发明授权

US06779139B2 Circuit for reducing test time and semiconductor memory device including the circuit 有权
标题翻译：降低测试时间的电路和包括电路的半导体存储器件
公开(公告)号：US06779139B2
公开(公告)日：2004-08-17
申请号：US09845494
申请日：2001-05-01
申请人： Masaru Haraguchi , Katsumi Dosaka , Tetsushi Tanizaki
发明人： Masaru Haraguchi , Katsumi Dosaka , Tetsushi Tanizaki
IPC分类号： G11C2900
CPC分类号： G11C29/44 , G01R31/318566 , G11C29/38
摘要： A semiconductor memory device includes: a determination section; an expected value control section; and an accumulation section. The determination section determines coincidence/non-coincidence between input data and an expected value. The expected value control section catches a read expected value in a read operation only. The accumulation section catches a determination result according to an accumulation-transmission signal. When the accumulation-transmission signal is in a transmission state, a determination result is caught, while when the accumulation-transmission signal enters an accumulation state, the next determination result is caught in a case of coincidence determination and once a non-coincidence determination result is caught, thereafter the non-coincidence determination result continues to be held.
摘要翻译：半导体存储器件包括：确定部分; 预期价值控制部分; 和积累部分。确定部分确定输入数据与期望值之间的一致/不一致。期望值控制部分仅在读取操作中捕获读取期望值。累积部根据累积发送信号来取得判定结果。当累积发送信号处于发送状态时，判断结果被捕获，而当累计发送信号进入累加状态时，在一致判断的情况下，下一个确定结果被捕获，并且一旦不一致确定结果被捕获，此后不合格确定结果继续保持。

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