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    • 7. 发明授权
    • Power gain reduction circuit for power amplifiers
    • 功率放大器的功率增益降低电路
    • US06842072B1
    • 2005-01-11
    • US10444751
    • 2003-05-23
    • Nai-Shuo ChengKevin ChoiPeter P. Tran
    • Nai-Shuo ChengKevin ChoiPeter P. Tran
    • H03G1/00H03G3/00H03G3/20
    • H03G3/004H03G1/0088
    • According to one exemplary embodiment, a gain reduction circuit comprises a first terminal, where the first terminal is coupled to a control signal. The gain reduction circuit further comprises a second terminal, where the second terminal is coupled to an input of an amplifier, and where the amplifier is configured to operate in low-power mode and high-power mode. The gain reduction circuit further comprises a transistor coupled to the first terminal and the second terminal. The transistor can be, for example, a bipolar transistor, such as an NPN GaAs heterojunction bipolar transistor, having a base, a collector, and an emitter, where the base being is coupled the control signal, the collector is coupled to the input of the amplifier, and the emitter is coupled to ground. According to this exemplary embodiment, the transistor causes a gain of the amplifier to be reduced when the amplifier is operating in low-power mode.
    • 根据一个示例性实施例,增益减小电路包括第一端子,其中第一端子耦合到控制信号。 增益减小电路还包括第二端子,其中第二端子耦合到放大器的输入,并且其中放大器被配置为在低功率模式和高功率模式下工作。 增益减小电路还包括耦合到第一端子和第二端子的晶体管。 晶体管可以是例如具有基极,集电极和发射极的诸如NPN GaAs异质结双极晶体管的双极晶体管,其中基极耦合控制信号,集电极耦合到 放大器和发射极耦合到地。 根据该示例性实施例,当放大器以低功率模式工作时,晶体管使放大器的增益减小。