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1. 发明授权

US06819565B2 Cavity-down ball grid array semiconductor package with heat spreader 失效
标题翻译：具有散热器的凹陷球栅阵列半导体封装
公开(公告)号：US06819565B2
公开(公告)日：2004-11-16
申请号：US10341711
申请日：2003-01-14
申请人： Nai-Hao Kao , Yu-Po Wang , Wen-Jung Chiang
发明人： Nai-Hao Kao , Yu-Po Wang , Wen-Jung Chiang
IPC分类号： H05K720
CPC分类号： H01L23/36 , H01L23/3128 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/05599 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2224/73265 , H01L2224/85413 , H01L2224/85444 , H01L2225/0651 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/00015 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader is provided, in which a substrate is formed with at least a ground ring, a plurality of ground vias, a ground layer, and at least an opening for receiving at least a chip. The substrate is mounted in a cavity of the heat spreader, and an electrically conductive adhesive is disposed between an inner wall of the cavity and edges of the substrate, so as to allow the ground layer and the ground ring exposed to the edges of the substrate to be electrically connected to the heat spreader by means of the electrically conductive adhesive. By the above arrangement with the heat spreader being included in a grounding circuit path of the chip, ground floatation and excess ground inductance and resistance can be prevented for the semiconductor package, thereby solving heat-dissipation, electromagnetic interference and crosstalk problems.
摘要翻译：提供了具有散热器的空腔向下球栅阵列（CDBGA）半导体封装，其中衬底形成有至少接地环，多个接地通孔，接地层和至少一个开口，用于在最小的芯片基板安装在散热器的空腔中，并且导电粘合剂设置在空腔的内壁和基板的边缘之间，以便使接地层和接地环暴露于基板的边缘通过导电粘合剂与散热器电连接。通过上述布置，散热器被包括在芯片的接地电路中，可以防止半导体封装的地面漂浮和多余的接地电感和电阻，从而解决散热，电磁干扰和串扰问题。

2. 发明授权

US08207620B2 Flip-chip semiconductor package and chip carrier for preventing corner delamination 有权
标题翻译：倒装芯片半导体封装和芯片载体，用于防止角分层
公开(公告)号：US08207620B2
公开(公告)日：2012-06-26
申请号：US11880467
申请日：2007-07-20
申请人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/29
CPC分类号： H01L21/563 , H01L24/31 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83951 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/351 , H01L2924/00
摘要： The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.
摘要翻译：本发明公开了一种倒装芯片半导体封装及其芯片载体。芯片载体包括围绕芯片安装区域形成的凹槽。槽可以沿着芯片安装区域的周边或其拐角处形成。凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。

3. 发明申请

US20080017983A1 Flip-chip semiconductor package and chip carrier thereof 有权
标题翻译：倒装芯片半导体封装及其芯片载体
公开(公告)号：US20080017983A1
公开(公告)日：2008-01-24
申请号：US11880467
申请日：2007-07-20
申请人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Yuan-Lin Tzeng , Nai-Hao Kao , Jeng-Yuan Lai , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/48
CPC分类号： H01L21/563 , H01L24/31 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83951 , H01L2924/01006 , H01L2924/01019 , H01L2924/01033 , H01L2924/01082 , H01L2924/19041 , H01L2924/19043 , H01L2924/3011 , H01L2924/351 , H01L2924/00
摘要： The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.
摘要翻译：本发明公开了一种倒装芯片半导体封装及其芯片载体。芯片载体包括围绕芯片安装区域形成的凹槽。槽可以沿着芯片安装区域的周边或其拐角处形成。凹槽填充有低杨氏模量的填料，以吸收和消除热应力，从而防止底部填充物和安装在芯片安装区域上的倒装芯片之间的分层。

4. 发明授权

US07732913B2 Semiconductor package substrate 有权
标题翻译：半导体封装基板
公开(公告)号：US07732913B2
公开(公告)日：2010-06-08
申请号：US11701767
申请日：2007-02-02
申请人： Tsung-Tien Hsieh , Wen-Jung Chiang , Yu-Po Wang , Cheng-Hsu Hsiao , Sen-Yen Yang
发明人： Tsung-Tien Hsieh , Wen-Jung Chiang , Yu-Po Wang , Cheng-Hsu Hsiao , Sen-Yen Yang
IPC分类号： H01L23/04
CPC分类号： H01L23/49827 , H01L23/64 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H05K1/0245 , H05K1/0251 , H05K1/114 , H05K3/429 , H05K2201/09236 , H05K2201/09636 , H05K2201/09718 , H01L2924/00
摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.
摘要翻译：提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

5. 发明授权

US07361846B2 High electrical performance semiconductor package 有权
标题翻译：高电性能半导体封装
公开(公告)号：US07361846B2
公开(公告)日：2008-04-22
申请号：US10974376
申请日：2004-10-26
申请人： Wen-Jung Chiang , Chien-Te Chen , Yu-Po Wang
发明人： Wen-Jung Chiang , Chien-Te Chen , Yu-Po Wang
IPC分类号： H05K1/16
CPC分类号： H01L23/49838 , H01L23/3677 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2224/49433 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.
摘要翻译：提出了一种高性能半导体封装。提供具有第一表面，相对的第二表面和用于将第一表面电连接到第二表面的导电通孔的载体。芯片附接到载体的第一表面。多个通孔焊盘周边设置在载体的第一表面上并电连接到通孔。多个导电区域设置在载体的第二表面上并电连接到通孔。多个指状物设置在芯片周围，并通过形成在载体的第一表面上的导电迹线电连接到通孔焊盘。多个接合线将芯片电连接到手指。用于传输差分对信号的导线的长度基本相等，用于发送差分对信号的迹线的长度基本相等。

6. 发明申请

US20070273026A1 Semiconductor package substrate 有权
标题翻译：半导体封装基板
公开(公告)号：US20070273026A1
公开(公告)日：2007-11-29
申请号：US11701767
申请日：2007-02-02
申请人： Hsieh-Tsung Tien , Wen-Jung Chiang , Yu-Po Wang , Cheng-Hsu Hsiao , Sen-Yen Yang
发明人： Hsieh-Tsung Tien , Wen-Jung Chiang , Yu-Po Wang , Cheng-Hsu Hsiao , Sen-Yen Yang
IPC分类号： H01L23/488
CPC分类号： H01L23/49827 , H01L23/64 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H05K1/0245 , H05K1/0251 , H05K1/114 , H05K3/429 , H05K2201/09236 , H05K2201/09636 , H05K2201/09718 , H01L2924/00
摘要： A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.
摘要翻译：提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

7. 发明申请

US20050253253A1 High electrical performance semiconductor package 有权
标题翻译：高电性能半导体封装
公开(公告)号：US20050253253A1
公开(公告)日：2005-11-17
申请号：US10974376
申请日：2004-10-26
申请人： Wen-Jung Chiang , Chien-Te Chen , Yu-Po Wang
发明人： Wen-Jung Chiang , Chien-Te Chen , Yu-Po Wang
IPC分类号： H01L23/10 , H01L23/367 , H01L23/498
CPC分类号： H01L23/49838 , H01L23/3677 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2224/49433 , H01L2924/00014 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.
摘要翻译：提出了一种高性能半导体封装。提供具有第一表面，相对的第二表面和用于将第一表面电连接到第二表面的导电通孔的载体。芯片附接到载体的第一表面。多个通孔焊盘周边设置在载体的第一表面上并电连接到通孔。多个导电区域设置在载体的第二表面上并电连接到通孔。多个指状物设置在芯片周围，并通过形成在载体的第一表面上的导电迹线电连接到通孔焊盘。多个接合线将芯片电连接到手指。用于传输差分对信号的导线的长度基本相等，用于发送差分对信号的迹线的长度基本相等。

8. 发明授权

US07629199B2 Method for fabricating semiconductor package with build-up layers formed on chip 有权
标题翻译：用于制造在芯片上形成积层的半导体封装的方法
公开(公告)号：US07629199B2
公开(公告)日：2009-12-08
申请号：US11713362
申请日：2007-03-01
申请人： Chien-Ping Huang , Yu-Po Wang
发明人： Chien-Ping Huang , Yu-Po Wang
IPC分类号： H01L21/00
CPC分类号： H01L24/10 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/24 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13 , H01L2224/13099 , H01L2224/20 , H01L2224/24227 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor package with build-up layers formed on a chip and a fabrication method of the semiconductor package are provided. A chip with a plurality of conductive bumps formed on bond pads thereof is received within a cavity of a carrier, and a dielectric layer encapsulates the conductive bumps whose ends are exposed. A plurality of conductive traces are formed on the dielectric layer and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with openings via which predetermined portions of the conductive traces are exposed and bonded to a plurality of solder balls. Thereby, positions of the bond pads are easily recognized and distinguished by the exposed ends of the conductive bumps, making the conductive traces capable of being well electrically connected through the conductive bumps to the bond pads to improve yield of the fabricated packages.
摘要翻译：提供了一种形成在芯片上的积层的半导体封装以及半导体封装的制造方法。在其接合焊盘上形成有多个导电凸块的芯片被容纳在载体的空腔内，并且介电层封装其端部露出的导电凸块。多个导电迹线形成在电介质层上并与导电凸块的端部电连接。焊接掩模层施加在导电迹线上并形成有开口，通过该开口，导电迹线的预定部分暴露并结合到多个焊球。因此，接合焊盘的位置容易地被导电凸块的露出端识别和区分，使得导电迹线能够通过导电凸块与接合焊盘良好地电连接，以提高制造的封装的产量。

9. 发明授权

US07271493B2 Semiconductor package free of substrate and fabrication method thereof 有权
标题翻译：不含衬底的半导体封装及其制造方法
公开(公告)号：US07271493B2
公开(公告)日：2007-09-18
申请号：US11112108
申请日：2005-04-21
申请人： Chien Ping Huang , Yu-Po Wang , Chih-Ming Huang
发明人： Chien Ping Huang , Yu-Po Wang , Chih-Ming Huang
IPC分类号： H01L29/40
CPC分类号： H01L21/4857 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/142 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/4985 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L24/97 , H01L2221/68345 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2224/81801 , H01L2224/85001 , H01L2224/85439 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/18165 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.
摘要翻译：提供一种半导体封装及其制造方法，其中使用形成有多个开口的电介质材料层，并且将焊料材料施加到每个开口中。第一铜层和第二铜层又沉积在介电材料层和焊料材料上，并且第一和第二铜层被图案化以形成多个导电迹线，每个导电迹线具有涂覆有金属层的端子。芯片安装在导电迹线上，并通过接合线电连接到端子，电介质材料层和焊料材料暴露于外部。该封装结构可以灵活地布置导电迹线并有效地缩短接合线，从而提高半导体封装的迹线布线性和电连接质量。

10. 发明申请

US20070164386A1 Semiconductor device and fabrication method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070164386A1
公开(公告)日：2007-07-19
申请号：US11648045
申请日：2006-12-28
申请人： Cheng-Yi Chang , Chien-Ping Huang , Yu-Po Wang , Chih-Ming Huang , Cheng-Hsu Hsiao
发明人： Cheng-Yi Chang , Chien-Ping Huang , Yu-Po Wang , Chih-Ming Huang , Cheng-Hsu Hsiao
IPC分类号： H01L31/0203 , H01L21/56
CPC分类号： H01L27/14687 , H01L24/97 , H01L27/14618 , H01L2224/48091 , H01L2224/48227 , H01L2224/8592 , H01L2224/97 , H01L2924/01033 , H01L2924/15311 , H01L2924/16195 , H01L2224/85 , H01L2924/00014
摘要： A semiconductor device and the fabrication method thereof are provided. The fabrication method includes providing a substrate module plate having a plurality of substrates; attaching at least one sensor chip to each of the substrates of the substrate module plate; electrically connecting each of the sensor chips to each of the substrates through bonding wires; forming an insulating layer between each sensor chip on the substrate module plate, wherein the height of the insulating layers are not greater than the thickness of the sensor chips so as to prevent flash from the insulating layers from contaminating the sensor chips; forming an adhesive lip on the insulating layer or forming a second insulating layer followed by forming the adhesive layer, wherein the adhesive layer or the second insulating layer is higher than the highest loop-height of the bonding wires; adhering a light transmitting cover to each adhesive layer to cover the sensor chip; and cutting the substrate module plate to separate the substrates to form a plurality of semiconductor devices each integrated with at least one sensor chip. As the adhesive layers are not in contact with the bonding wires, the problems of damaging or breaking the bonding wires can be prevented in the process of adhering the light transmitting cover.
摘要翻译：提供半导体器件及其制造方法。该制造方法包括提供具有多个基板的基板模块板; 将至少一个传感器芯片附接到所述基板模块板的每个基板; 通过接合线将每个传感器芯片电连接到每个基板; 在衬底模块板上的每个传感器芯片之间形成绝缘层，其中绝缘层的高度不大于传感器芯片的厚度，以防止来自绝缘层的闪光污染传感器芯片; 在所述绝缘层上形成粘合剂唇缘或形成第二绝缘层，接着形成所述粘合剂层，其中所述粘合剂层或所述第二绝缘层高于所述接合线的最高环高度; 将透光盖粘附到每个粘合剂层以覆盖传感器芯片; 以及切割所述基板模块板以分离所述基板以形成多个半导体器件，每个半导体器件与至少一个传感器芯片集成。由于粘合层不与接合线接触，所以在粘接透光罩的过程中可以防止损坏或断裂接合线的问题。

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