专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08124880B2 Circuit board and method for manufacturing thereof 有权
标题翻译：电路板及其制造方法
公开(公告)号：US08124880B2
公开(公告)日：2012-02-28
申请号：US11976207
申请日：2007-10-22
申请人： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
发明人： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
IPC分类号： H05K1/03
CPC分类号： H05K1/0265 , H05K1/116 , H05K3/107 , H05K3/108 , H05K3/205 , H05K3/421 , H05K2201/0379 , H05K2201/0394 , H05K2201/09509 , H05K2201/09736 , H05K2203/0361
摘要： A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.
摘要翻译：一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

2. 发明申请

US20110221074A1 Board on chip package 审中-公开
标题翻译：板上封装
公开(公告)号：US20110221074A1
公开(公告)日：2011-09-15
申请号：US13067219
申请日：2011-05-17
申请人： Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
发明人： Myung-Sam Kang , Chang-Sup Ryu , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
IPC分类号： H01L23/488
CPC分类号： H01L23/3128 , H01L21/568 , H01L21/6835 , H01L23/13 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2221/68345 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/81801 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/30105 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A board on chip package including a photo solder resist having a cavity and a pattern on one side, the pattern corresponding to a circuit wire; a solder ball pad accommodated in the cavity; a circuit wire electrically connected with the solder ball pad, and formed on the other side of the photo solder resist; a semiconductor chip mounted on the solder ball pad by a flip chip bonding; and a passivation material to mold the semiconductor chip.
摘要翻译：一种片上封装，包括具有空腔和一侧图案的光阻焊剂，该图案对应于电路线; 容纳在腔中的焊球垫; 与焊锡球焊盘电连接并形成在光阻焊剂的另一侧上的电路线; 通过倒装芯片焊接安装在焊球垫上的半导体芯片; 以及用于模制半导体芯片的钝化材料。

3. 发明申请

US20080098597A1 Method of manufacturing circuit board 有权
标题翻译：电路板制造方法
公开(公告)号：US20080098597A1
公开(公告)日：2008-05-01
申请号：US11976072
申请日：2007-10-19
申请人： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
发明人： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
IPC分类号： H05K3/02
CPC分类号： H05K3/20 , H05K3/0058 , H05K3/108 , H05K3/4611 , H05K3/4682 , H05K2201/0394 , H05K2201/09481 , H05K2201/09518 , H05K2201/09563 , H05K2203/0152 , H05K2203/0376 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
摘要： A method of manufacturing a circuit board is disclosed. A method of manufacturing a circuit board that includes forming a first circuit pattern on the insulation layer of a carrier, in which an insulation layer and a first seed layer are stacked in order; stacking and pressing the carrier and an insulation board with the side of the carrier having the first circuit pattern facing the insulation board; removing the carrier to transfer the first circuit pattern and the insulation layer onto the insulation board; and forming a second circuit pattern on the insulation layer transferred to the insulation board, allows fine pitch circuit patterns to enable the manufacture of fine circuit patterns of high density on the board, and allows the manufacture of a multi-layer circuit board with a simple process.
摘要翻译：公开了一种制造电路板的方法。一种制造电路板的方法，包括在载体的绝缘层上形成第一电路图案，其中绝缘层和第一种子层依次层叠; 堆叠并按压载体和绝缘板，其中载体侧具有面向绝缘板的第一电路图案; 移除载体以将第一电路图案和绝缘层转移到绝缘板上; 并且在转移到绝缘板的绝缘层上形成第二电路图案，允许精细的间距电路图案能够在板上制造高密度的精细电路图案，并且允许制造具有简单的多层电路板处理。

4. 发明授权

US08197702B2 Manufacturing method of printed circuit board 有权
标题翻译：印刷电路板的制造方法
公开(公告)号：US08197702B2
公开(公告)日：2012-06-12
申请号：US12508224
申请日：2009-07-23
申请人： Myung-Sam Kang , Jung-Hyun Park , Ji-Eun Kim
发明人： Myung-Sam Kang , Jung-Hyun Park , Ji-Eun Kim
IPC分类号： C25D5/02 , B32B37/00 , B32B38/00
CPC分类号： B32B37/02 , B32B2457/08 , C25D5/022 , H05K3/205 , H05K3/428 , H05K3/4658 , H05K2201/0376 , H05K2203/0384
摘要： Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for interlayer connection can include forming a circuit pattern on one side of a carrier, pressing one side of the carrier into one side of the insulator, removing the carrier, forming a hole penetrating through the insulator by processing one end of the circuit pattern, and forming a conductive material inside the hole to have the conductive material correspond to the via.
摘要翻译：公开了印刷电路板的制造方法。制造具有用于层间连接的通孔的印刷电路板的方法可以包括在载体的一侧上形成电路图案，将载体的一侧压在绝缘体的一侧，去除载体，形成贯穿该载体的孔通过处理电路图案的一端，并且在孔内形成导电材料以使导电材料对应于通孔。

5. 发明申请

US20100255634A1 Manufacturing method of bottom substrate of package 审中-公开
标题翻译：封装底部基板的制造方法
公开(公告)号：US20100255634A1
公开(公告)日：2010-10-07
申请号：US12801574
申请日：2010-06-15
申请人： Jung-Hyun Park , Byoung-Youl Min , Je-Gwang Yoo , Myung-Sam Kang , Hoe-Ku Jung , Ji-Eun Kim
发明人： Jung-Hyun Park , Byoung-Youl Min , Je-Gwang Yoo , Myung-Sam Kang , Hoe-Ku Jung , Ji-Eun Kim
IPC分类号： H01L21/60 , H01L21/50
CPC分类号： H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06568 , H01L2225/06586 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A manufacturing method of bottom substrate of package. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.
摘要翻译：封装底部基板的制造方法。封装的封装的底部衬底通过焊球电连接到顶部衬底，所述焊球包括芯板，与所述焊球的位置对应地形成在所述芯板的表面上的焊球焊盘，绝缘体层叠在芯板上的通孔，通过去除绝缘层的一部分使得焊球焊盘露出而形成的通孔以及填充在通孔中并与焊球电连接的金属层允许IC的数量安装在底部基板上以增加焊球的尺寸，并且通过控制层叠在底部基板上的绝缘层的厚度，可以使焊球的尺寸和间距变小，由此更多的信号传输是可能在顶部基板和底部基板之间。

6. 发明申请

US20080264676A1 Circuit board and method for manufaturing thereof 有权
标题翻译：电路板及其制造方法
公开(公告)号：US20080264676A1
公开(公告)日：2008-10-30
申请号：US11976207
申请日：2007-10-22
申请人： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
发明人： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
IPC分类号： H05K1/00
CPC分类号： H05K1/0265 , H05K1/116 , H05K3/107 , H05K3/108 , H05K3/205 , H05K3/421 , H05K2201/0379 , H05K2201/0394 , H05K2201/09509 , H05K2201/09736 , H05K2203/0361
摘要： A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.
摘要翻译：一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

7. 发明申请

US20080251494A1 Method for manufacturing circuit board 审中-公开
标题翻译：电路板制造方法
公开(公告)号：US20080251494A1
公开(公告)日：2008-10-16
申请号：US12078058
申请日：2008-03-26
申请人： Jung-Hyun Park , Byoung-Youl Min , Jeong-Woo Park , Jong-Gyu Choi , Ji-Eun Kim , Myung-Sam Kang
发明人： Jung-Hyun Park , Byoung-Youl Min , Jeong-Woo Park , Jong-Gyu Choi , Ji-Eun Kim , Myung-Sam Kang
IPC分类号： H01B13/00 , C25D5/34
CPC分类号： C25D7/123 , H05K3/0038 , H05K3/108 , H05K3/205 , H05K3/421 , H05K3/423 , H05K2201/0376 , H05K2201/0394 , H05K2201/09563 , H05K2203/108
摘要： A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed.
摘要翻译：公开了一种制造电路板的方法。该方法可以包括：在层叠在载体上的金属层上形成与电路图案对应关系的释放图案; 将载体堆叠并压制到绝缘层上，其中减震图案面向绝缘层; 通过移除载体将金属层和释放图案转印到绝缘层中; 在所述绝缘层上形成通孔，所述绝缘层中所述金属层被转录到所述绝缘层上; 并通过在其上转印有金属层的绝缘层上进行电镀来填充通孔并在金属层上形成镀层。由于可以在堆叠在载体上的金属层上形成缓和图案，并且可以将缓冲图案转录到绝缘层中，可以形成高密度电路图案。

8. 发明申请

US20080009128A1 Buried pattern substrate and manufacturing method thereof 审中-公开
标题翻译：埋地图案基板及其制造方法
公开(公告)号：US20080009128A1
公开(公告)日：2008-01-10
申请号：US11708339
申请日：2007-02-21
申请人： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
发明人： Shuhichi Okabe , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Ji-Eun Kim
IPC分类号： H01L21/44
CPC分类号： H05K3/205 , H05K3/4038 , H05K3/4617 , H05K2203/0733 , H05K2203/1572
摘要： A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by depositing a plating layer selectively on a seed layer of a carrier film, where the seed layer is laminated on a surface of the carrier film, (b) laminating and pressing the carrier film on an insulation layer such that the circuit pattern and the stud bump face the insulation layer, and (c) removing the carrier film and the seed layer, allows the circuit interconnection to be realized using a copper (Cu) stud bump, so that a drilling process for interconnection is unnecessary, the degree of freedom for circuit design is improved, a via land is made unnecessary and the size of a via is small, to allow higher density in a circuit.
摘要翻译：公开了掩埋图案基板及其制造方法。一种制造埋设图形衬底的方法，其中电路图案形成在电路图形通过柱形凸块电连接的表面上，包括：（a）通过在晶种层层叠在载体膜的表面上的载体膜的种子层，（b）在绝缘层上层叠压制载体膜，使得电路图案和柱状凸块面向绝缘层，和 c）去除载体膜和种子层，允许使用铜（Cu）柱状凸块实现电路互连，使得不需要用于互连的钻孔工艺，提高了电路设计的自由度，通孔焊盘不必要，并且通孔的尺寸小，以允许电路中的较高密度。

9. 发明申请

US20120111607A1 CIRCUIT BOARD WITH HIGH-DENSITY CIRCUIT PATTERNS 有权
标题翻译：具有高密度电路图形的电路板
公开(公告)号：US20120111607A1
公开(公告)日：2012-05-10
申请号：US13354438
申请日：2012-01-20
申请人： Shuhichi OKABE , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
发明人： Shuhichi OKABE , Myung-Sam Kang , Jung-Hyun Park , Hoe-Ku Jung , Jeong-Woo Park , Ji-Eun Kim
IPC分类号： H05K1/02
CPC分类号： H05K1/0265 , H05K1/116 , H05K3/107 , H05K3/108 , H05K3/205 , H05K3/421 , H05K2201/0379 , H05K2201/0394 , H05K2201/09509 , H05K2201/09736 , H05K2203/0361
摘要： A circuit board including: an insulator having a trench; a first circuit pattern formed to bury a portion of the trench; and a second circuit pattern formed on a surface of the insulator having the trench formed therein.
摘要翻译：一种电路板，包括：具有沟槽的绝缘体; 形成为埋入沟槽的一部分的第一电路图案; 以及形成在其中形成有沟槽的绝缘体的表面上的第二电路图案。

10. 发明授权

US07992291B2 Method of manufacturing a circuit board 有权
标题翻译：制造电路板的方法
公开(公告)号：US07992291B2
公开(公告)日：2011-08-09
申请号：US11976070
申请日：2007-10-19
申请人： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
发明人： Hoe-Ku Jung , Je-Gwang Yoo , Myung-Sam Kang , Ji-Eun Kim , Jeong-Woo Park , Jung-Hyun Park
IPC分类号： H05K3/20 , H05K1/18
CPC分类号： H05K3/205 , H01L21/4846 , H01L23/49816 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/15311 , H05K3/4007 , H05K2201/09745 , H05K2201/10674 , H05K2203/0338 , H05K2203/0435 , Y10T29/49126 , Y10T29/49128 , Y10T29/49144 , Y10T29/49149 , Y10T29/49155 , Y10T29/49165
摘要： A method of manufacturing a circuit board, which includes a bump pad on which a solder bump may be placed, may include forming a solder pad on a surface of a first carrier; forming a metal film, which covers the solder pad and which extends to a bump pad forming region; forming a circuit layer and a circuit pattern, which are electrically connected with the metal film, on a surface of the first carrier; pressing the first carrier and an insulator such that a surface of the first carrier and the insulator faces each other; and removing the first carrier. Utilizing this method, the amount of solder for the contacting of a flip chip can be adjusted, and solder can be filled inside the board, so that after installing a chip, the overall thickness of the package can be reduced.
摘要翻译：一种制造电路板的方法，包括可以放置焊锡凸块的凸块焊盘，可以包括在第一载体的表面上形成焊盘; 形成覆盖焊盘并延伸到凸块焊盘形成区域的金属膜; 在所述第一载体的表面上形成与所述金属膜电连接的电路层和电路图案; 按压所述第一载体和绝缘体，使得所述第一载体和所述绝缘体的表面彼此面对; 并移除第一载体。利用这种方法，可以调节用于接合倒装芯片的焊料的量，并且可以在板内填充焊料，使得在安装芯片之后，可以减小封装的整体厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式