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1. 发明授权

US06192160B1 Hardware architectures for image dilation and erosion operations 失效
标题翻译：用于图像扩张和侵蚀操作的硬件架构
公开(公告)号：US06192160B1
公开(公告)日：2001-02-20
申请号：US08932132
申请日：1997-09-18
申请人： Myung Hoon Sunwoo , Soohwan Ong , Eul-suk Lee , Tae-Young Choi
发明人： Myung Hoon Sunwoo , Soohwan Ong , Eul-suk Lee , Tae-Young Choi
IPC分类号： G06K942
CPC分类号： G06K9/44 , G06T5/30
摘要： A hardware architecture for mathematical morphology operations such as dilation and erosion of an image signal is provided. A hardware architecture for an image dilation operation includes: a plurality of adders corresponding to the size of the structuring element for adding the image signal and a structuring element symmetrical to the image signal with respect to the origin to output the result; a plurality of stores for temporarily storing the signals output from the plural adders; a comparator for comparing data stored in the plural stores with feedback data to output the maximum data; and an outputting device for outputting the output signal of the comparator as a dilation operation value if the dilation operation with respect to all structuring elements for one image signal is completed and feeding back the output signal of the comparator as input data of the comparator if not. Therefore, the elementary operations such as dilation and erosion with respect to a gray-level image signal can be attained by a simple arithmetic operation, that is, by finding the maximum/minimum value using an adder. Also, since the hardware architecture for the dilation and erosion operations adopts a feedback structure, the volume of the hardware linearly increases even though the size of the structuring element increases in geometrical progression.
摘要翻译：提供了用于数学形态学操作的硬件结构，例如图像信号的扩张和侵蚀。用于图像扩张操作的硬件结构包括：对应于用于添加图像信号的结构元素的大小的多个加法器和与图像信号相对于原点对称的结构元素以输出结果; 多个存储器，用于临时存储从多个加法器输出的信号; 用于将存储在多个存储器中的数据与反馈数据进行比较以输出最大数据的比较器; 以及输出装置，用于如果相对于一个图像信号的所有结构元素的扩张操作完成并输出比较器的输出信号作为扩张操作值，并且将比较器的输出信号作为比较器的输入数据反馈。因此，通过简单的算术运算即通过使用加法器求出最大/最小值，可以获得关于灰度图像信号的基本运算，例如扩大和侵蚀。此外，由于用于扩张和侵蚀操作的硬件架构采用反馈结构，即使结构元件的尺寸在几何进程中增加，硬件的体积线性增加。

2. 发明授权

US08200730B2 Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors 有权
标题翻译：用于在可编程处理器上运行MPEG-2 AAC或MPEG-4AAC音频解码算法的计算电路和方法
公开(公告)号：US08200730B2
公开(公告)日：2012-06-12
申请号：US12880720
申请日：2010-09-13
申请人： Jong Hoon Oh , Myung Hoon Sunwoo , Jong Ha Moon
发明人： Jong Hoon Oh , Myung Hoon Sunwoo , Jong Ha Moon
IPC分类号： G06F17/14
CPC分类号： G10L19/16
摘要： The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.
摘要翻译：本发明涉及用于在可编程处理器上用作多声道高质量音频系统中的音频压缩算法的有效运行MPEG-2AAC或MPEG-4AAC算法的计算电路和方法。根据本发明，可以有效地执行在实施MPEG-2 / 4AAC算法中占用大量部分操作的IMDCT处理。另外，虽然现有的数字信号处理器的架构仍然被使用，但是通过添加地址生成器，霍夫曼解码器和位处理架构的架构，可以提高性能。毕竟，设计和改变可编程处理器是方便的。

3. 发明授权

US09317934B2 Method and apparatus for estimating motion 有权
标题翻译：估计运动的方法和装置
公开(公告)号：US09317934B2
公开(公告)日：2016-04-19
申请号：US14355095
申请日：2012-10-19
申请人： Myung Hoon Sunwoo , Ho Il Bang
发明人： Myung Hoon Sunwoo , Ho Il Bang
IPC分类号： H04N7/50 , G06T9/00 , H04N19/56 , H04N19/105 , H04N19/176 , H04N19/119 , H04N19/154 , H04N19/436 , H04N7/26
CPC分类号： G06T9/00 , H04N19/105 , H04N19/119 , H04N19/154 , H04N19/176 , H04N19/436 , H04N19/56
摘要： Provided are a motion estimation method and a motion estimation apparatus. The motion estimation apparatus includes a first register storing information on whether to detect first detection positions, a second register storing information on distances and number information of valid distance information, a controller receiving a command, a shifter, in response to the shift-enable signal, shifting and outputting reference data in a detection region of a reference frame and outputting the received reference data as it is, a selector, in response to the selection signal, selecting and outputting a part of output data of the shifter or outputting the whole output data, a process element (PE) array receiving current data of a current frame, and a comparator generating operation results for respective block sizes using operation results of the plurality of the PEGs.
摘要翻译：提供了一种运动估计方法和运动估计装置。运动估计装置包括：第一寄存器，存储关于是否检测第一检测位置的信息;第二寄存器，存储关于距离的信息和有效距离信息的数量信息;控制器，接收命令，移位器，响应于移位使能信号，在参考帧的检测区域中移位并输出参考数据，并原样输出接收到的参考数据，选择器，响应于选择信号，选择并输出移位器的输出数据的一部分或输出整个输出数据，接收当前帧的当前数据的处理元件（PE）阵列，以及比较器，使用多个PEG的操作结果产生各个块大小的运算结果。

4. 发明授权

US07805477B2 Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors 有权
标题翻译：用于在可编程处理器上运行MPEG-2 AAC或MPEG-4AAC音频解码算法的计算电路和方法
公开(公告)号：US07805477B2
公开(公告)日：2010-09-28
申请号：US11342765
申请日：2006-01-30
申请人： Jong Hoon Oh , Myung Hoon Sunwoo , Jong Ha Moon
发明人： Jong Hoon Oh , Myung Hoon Sunwoo , Jong Ha Moon
IPC分类号： G06F17/14
CPC分类号： G10L19/16
摘要： The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.
摘要翻译：本发明涉及用于在可编程处理器上用作多声道高质量音频系统中的音频压缩算法的有效运行MPEG-2AAC或MPEG-4AAC算法的计算电路和方法。根据本发明，可以有效地执行在实施MPEG-2 / 4AAC算法中占用大量部分操作的IMDCT处理。另外，虽然现有的数字信号处理器的架构仍然被使用，但通过添加地址生成器，霍夫曼解码器和位处理架构的架构，可以提高性能。毕竟，设计和改变可编程处理器是方便的。

5. 发明授权

US07333036B2 Computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC audio decoding algorithm on programmable processors 有权
标题翻译：用于在可编程处理器上运行MPEG-2 AAC或MPEG-4AAC音频解码算法的计算电路和方法
公开(公告)号：US07333036B2
公开(公告)日：2008-02-19
申请号：US11342764
申请日：2006-01-30
申请人： Jong Hoon Oh , Myung Hoon Sunwoo , Jong Ha Moon
发明人： Jong Hoon Oh , Myung Hoon Sunwoo , Jong Ha Moon
IPC分类号： H03M7/40
CPC分类号： H03M7/40 , G10L19/16
摘要： The present invention relates to the computing method and Huffman computing circuits for improving the correctness and efficiency of the nonlinear inverse quantization when the MPEG-2 AAC (Advanced Audio Coding) or MPEG-4 AAC algorithm which is used as an audio compression algorithm in multi-channel high-quality audio systems is implemented on programmable processors. In accordance with the present invention, while the architecture of the existing digital signal processor is reused, the performance can be improved by means of the addition of Huffman decoder and bit processing architecture. Accordingly, to design and change the programmable processor can be facilitated.
摘要翻译：本发明涉及当用作多声道压缩算法的MPEG-2AAC（高级音频编码）或MPEG-4AAC算法时，用于提高非线性逆量化的正确性和效率的计算方法和霍夫曼计算电路通道高品质音频系统在可编程处理器上实现。根据本发明，在现有的数字信号处理器的结构被重用的同时，通过加入霍夫曼解码器和比特处理架构可以提高性能。因此，可以方便设计和改变可编程处理器。

6. 发明申请

US20110150143A1 SOFT-DECISION DEMAPPING METHOD FOR DIGITAL SIGNAL 审中-公开
标题翻译：数字信号的软决策解决方法
公开(公告)号：US20110150143A1
公开(公告)日：2011-06-23
申请号：US12915449
申请日：2010-10-29
申请人： Jae Hee Han , Pan Soo Kim , Dae Ig Chang , Jang Woong Park , Myung Hoon Sunwoo
发明人： Jae Hee Han , Pan Soo Kim , Dae Ig Chang , Jang Woong Park , Myung Hoon Sunwoo
IPC分类号： H04L27/22
CPC分类号： H04L25/067 , H04L27/38
摘要： Disclosed is a demapping method of a soft-decision of an efficient soft determining scheme which is applicable to a DVB-2 satellite communication system. The soft-decision demapping method for a digital signal received through a transmission channel in a communication system using a phase shift keying (PSK) scheme includes: selecting reference symbols in an area having a higher probability than a predetermined probability that the received signal will be positioned among all reference symbols on a constellation diagram using a most significant bit (MSB) value of the received signal; and acquiring a maximum value of a log likelihood ratio (LLR) for the selected reference symbols.
摘要翻译：公开了一种适用于DVB-2卫星通信系统的有效软确定方案的软判决的解映射方法。在使用相移键控（PSK）方式的通信系统中通过传输信道接收的数字信号的软判决解映射方法包括：在具有比接收信号将要的预定概率更高的概率的区域中选择参考符号使用接收信号的最高有效位（MSB）值在星座图上位于所有参考符号之间; 并获取所选参考符号的对数似然比（LLR）的最大值。

7. 发明申请

US20100138878A1 RECEIVER CIRCUIT OF SATELLITE DIGITAL VIDEO BROADCAST SYSTEM 审中-公开
标题翻译：卫星数字视频广播系统的接收电路
公开(公告)号：US20100138878A1
公开(公告)日：2010-06-03
申请号：US12629522
申请日：2009-12-02
申请人： Pan Soo Kim , Joon Gyu Ryu , Dae Ig Chang , Ho Jin Lee , Myung Hoon Sunwoo , Jin Kyu Choi
发明人： Pan Soo Kim , Joon Gyu Ryu , Dae Ig Chang , Ho Jin Lee , Myung Hoon Sunwoo , Jin Kyu Choi
IPC分类号： H04N7/20 , H04B1/707
CPC分类号： H04N7/20
摘要： A receiver circuit of a satellite digital video broadcast system includes: a multiplication unit outputting a synchronized reception symbol by multiplying a reception symbol by frequency error information as a feedback; a common autocorrelation unit acquiring autocorrelation values for each symbol by multiplying the synchronized reception symbol by an autocorrelation coefficient; a frame synchronization unit detecting a SOF (Start Of Frame), which is a synchronization word indicating start of a frame, from the autocorrelation values for each symbol; a frequency synchronization unit estimating the frequency error information based on the autocorrelation values for each reception symbol and the SOF; and an SNR estimation unit estimating an SNR (Signal to Noise Ratio) based on the autocorrelation values for each symbol and the SOF.
摘要翻译：卫星数字视频广播系统的接收机电路包括：乘法单元，通过将接收符号乘以频率误差信息作为反馈来输出同步的接收符号; 公共自相关单元通过将同步接收符号乘以自相关系数来获取每个符号的自相关值; 从每个符号的自相关值中检测作为指示帧起始的同步字的SOF（帧起点）的帧同步单元; 频率同步单元，基于每个接收符号和所述SOF的自相关值估计所述频率误差信息; 以及SNR估计单元，基于每个符号和SOF的自相关值来估计SNR（信噪比）。

8. 发明授权

US06314129B1 Circuit and method for timing recovery in digital communication receiver 失效
标题翻译：数字通信接收机定时恢复电路及方法
公开(公告)号：US06314129B1
公开(公告)日：2001-11-06
申请号：US09195508
申请日：1998-11-18
申请人： Myung Hoon Sunwoo , Se Young Eun
发明人： Myung Hoon Sunwoo , Se Young Eun
IPC分类号： H04L2730
CPC分类号： H04B1/7085 , H04B1/7093 , H04L7/0274 , H04L7/042
摘要： Circuit and method for timing recovery in a digital communication receiver for improving a BER performance and having a faster data transmission rate, the timing recovery circuit for recovering a synchronous timing signal of a PN code from an output of a matched filter in the digital communication receiver, including a power calculation circuit for receiving an output of the matched filter and calculating a power of a PN code signal for each sample period in each symbol period, a maximal power position detection circuit for detecting a sample position at which a symbol period has a maximum power value, a symbol position tracking circuit for tracking and setting an optimal symbol position value, a modulo counter for rotating as many as a number of samples in one symbol period in counting the samples for providing a reference position of samples, and a comparator for comparing the present symbol position value from the symbol position tracking circuit and a count value from the modulo counter, and generating a symbol clock when the present symbol position value and the count value are the same.
摘要翻译：用于提高BER性能并具有更快数据传输速率的用于数字通信接收机中的定时恢复的电路和方法，用于从数字通信接收机中的匹配滤波器的输出恢复PN码的同步定时信号的定时恢复电路包括功率计算电路，用于接收匹配滤波器的输出并且在每个符号周期内为每个采样周期计算PN码信号的功率;最大功率位置检测电路，用于检测符号周期具有的采样位置最大功率值，用于跟踪和设置最佳符号位置值的符号位置跟踪电路，用于在对用于提供样本的参考位置的采样进行计数的一个符号周期中旋转多达多个样本的模数计数器，以及比较器用于比较来自符号位置跟踪电路的当前符号位置值和来自模co的计数值并且当当前符号位置值和计数值相同时产生符号时钟。

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