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1. 发明授权

US09941196B2 Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device 有权
公开(公告)号：US09941196B2
公开(公告)日：2018-04-10
申请号：US15130904
申请日：2016-04-15
申请人： Ho-Jin Lee , Tae-Je Cho , Dong-Hyeon Jang , Ho-Geon Song , Se-Young Jeong , Un-Byoung Kang , Min-Seung Yoon
发明人： Ho-Jin Lee , Tae-Je Cho , Dong-Hyeon Jang , Ho-Geon Song , Se-Young Jeong , Un-Byoung Kang , Min-Seung Yoon
IPC分类号： H01L21/768 , H01L23/498 , H01L23/48 , H01L25/065 , H01L23/525
CPC分类号： H01L23/49844 , H01L21/76831 , H01L21/76844 , H01L21/76898 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/525 , H01L25/0657 , H01L2224/02372 , H01L2224/05009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06544 , H01L2924/15311
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

2. 发明授权

US09852965B2 Semiconductor devices with through electrodes and methods of fabricating the same 有权
公开(公告)号：US09852965B2
公开(公告)日：2017-12-26
申请号：US15204632
申请日：2016-07-07
申请人： Ho-Jin Lee , Byung Lyul Park , Kwangjin Moon , Jisoon Park , Jin Ho An
发明人： Ho-Jin Lee , Byung Lyul Park , Kwangjin Moon , Jisoon Park , Jin Ho An
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L21/76898 , H01L2224/11 , H01L2224/16145 , H01L2924/181 , H01L2924/00012
摘要： Provided herein are semiconductor devices with through electrodes and methods of fabricating the same. The methods may include providing a semiconductor substrate having top and bottom surfaces facing each other, forming on the top surface of the semiconductor substrate a main via having a hollow cylindrical structure and a metal line connected to the main via, forming an interlayered insulating layer on the top surface of the semiconductor substrate to cover the main via and the metal line, removing a portion of the semiconductor substrate to form a via hole exposing a portion of a bottom surface of the main via, and forming in the via hole a through electrode that is electrically connected to the main via. The bottom surface of the main via is overlapped by a circumference of the via hole, when viewed in a plan view.

3. 发明授权

US09219035B2 Integrated circuit chips having vertically extended through-substrate vias therein 有权
标题翻译：集成电路芯片，其中具有垂直延伸的穿过基板的通孔
公开(公告)号：US09219035B2
公开(公告)日：2015-12-22
申请号：US14153478
申请日：2014-01-13
申请人： Ho-jin Lee , Kang-wook Lee , Myeong-soon Park , Ju-il Choi , Son-kwan Hwang
发明人： Ho-jin Lee , Kang-wook Lee , Myeong-soon Park , Ju-il Choi , Son-kwan Hwang
IPC分类号： H01L23/48 , H01L23/528 , H01L21/768 , H01L25/065 , H01L25/00 , H01L23/522
CPC分类号： H01L23/528 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/06181 , H01L2224/13009 , H01L2224/16145 , H01L2224/16225 , H01L2224/48145 , H01L2225/06513 , H01L2225/06541 , H01L2924/15311 , H01L2924/00012
摘要： Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.
摘要翻译：形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。第一侧壁间隔层形成在互连孔的侧壁上。在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。然后用通孔电极填充互连孔和未切割凹部。去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

4. 发明申请

US20150279825A1 SEMICONDUCTOR DEVICES HAVING HYBRID STACKING STRUCTURES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：具有混合堆叠结构的半导体器件及其制造方法
公开(公告)号：US20150279825A1
公开(公告)日：2015-10-01
申请号：US14669291
申请日：2015-03-26
申请人： Pil-Kyu KANG , Byung Lyul PARK , Taeyeong KIM , Yeun-Sang PARK , Dosun LEE , Ho-Jin LEE , Jinho CHUN , Ju-il CHOI , Yi Koan HONG
发明人： Pil-Kyu KANG , Byung Lyul PARK , Taeyeong KIM , Yeun-Sang PARK , Dosun LEE , Ho-Jin LEE , Jinho CHUN , Ju-il CHOI , Yi Koan HONG
IPC分类号： H01L25/16 , H01L23/538 , H01L23/495 , H01L21/48 , H01L21/768 , H01L21/66 , H01L25/00 , H01L21/304
CPC分类号： H01L25/50 , H01L21/304 , H01L21/561 , H01L21/76898 , H01L22/32 , H01L23/3128 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/05568 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/06181 , H01L2224/08146 , H01L2224/131 , H01L2224/13124 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/81191 , H01L2224/81193 , H01L2224/9202 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06565 , H01L2225/06596 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/81 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.
摘要翻译：提供具有芯片堆叠和互连端子的半导体器件。芯片堆叠包括彼此堆叠的第一半导体芯片，第二半导体芯片和第三半导体芯片。互连端子电耦合到芯片堆叠。第一半导体芯片包括第一正面和第一背面。第二半导体芯片包括电耦合到第二电路层并穿透第二半导体芯片的第二前表面，第二背面，第二电路层和贯通电极。第三半导体芯片包括第三前表面，与第三前表面相对的第三背面和与第三前表面相邻的第三电路层。第一前表面和第二前表面彼此面对。第三前表面和第二后侧表面彼此面对。

5. 发明授权

US08878215B2 Light emitting device module 有权
标题翻译：发光装置模块
公开(公告)号：US08878215B2
公开(公告)日：2014-11-04
申请号：US13412820
申请日：2012-03-06
申请人： Jun Seok Park , Ho Jin Lee
发明人： Jun Seok Park , Ho Jin Lee
IPC分类号： H01L33/60 , H01L33/52
CPC分类号： H01L33/54 , H01L33/002 , H01L33/06 , H01L33/10 , H01L33/44 , H01L33/48 , H01L33/483 , H01L33/507 , H01L33/52 , H01L33/58 , H01L33/62 , H01L33/644 , H01L2224/48091 , H01L2224/73265 , H01L2924/00014
摘要： Disclosed is a light emitting device module. The light emitting device module includes a first lead frame and a second lead frame electrically separated from each other, a light emitting device electrically connected to the first lead frame and the second lead frame, the light emitting device includes a light emitting structure having a first conduction type semiconductor layer, an active layer, and a second conduction type semiconductor layer, a dam disposed at the peripheral area of the light emitting device, a resin layer surrounding the light emitting device and disposed at the inner area of the dam, and a reflective member disposed at the peripheral area of the dam and including an inclined plane formed on at least one side surface thereof.
摘要翻译：公开了一种发光器件模块。发光器件模块包括彼此电分离的第一引线框架和第二引线框架，电连接到第一引线框架和第二引线框架的发光器件，发光器件包括发光结构，其具有第一导电型半导体层，有源层和第二导电型半导体层，设置在发光器件的周边区域的堤坝，围绕发光器件并设置在坝的内部区域的树脂层，以及反射构件设置在坝的周边区域并且包括形成在其至少一个侧表面上的倾斜平面。

6. 发明授权

US08619859B2 Motion estimation apparatus and method and image encoding apparatus and method employing the same 有权
标题翻译：运动估计装置及方法及图像编码装置及方法
公开(公告)号：US08619859B2
公开(公告)日：2013-12-31
申请号：US11779415
申请日：2007-07-18
申请人： Sang-jo Lee , Ho-jin Lee , Do-hyung Kim
发明人： Sang-jo Lee , Ho-jin Lee , Do-hyung Kim
IPC分类号： H04N7/12
CPC分类号： H04N19/57 , H04N19/51 , H04N19/533 , H04N19/56
摘要： Provided are a motion estimation apparatus and method and an image encoding apparatus and method employing the same. The motion estimation apparatus includes an optimal motion estimation unit performing motion estimation in an initial block mode while skipping remaining block modes excluding the initial block mode from a plurality of block modes of the current block, or performing motion estimation in candidate block modes determined from the plurality of block modes.
摘要翻译：提供了一种运动估计装置和方法以及采用该运动估计装置和方法的图像编码装置和方法。运动估计装置包括：最优运动估计单元，在从当前块的多个块模式中跳过除了初始块模式之外的剩余块模式时，以初始块模式执行运动估计，或者在从所述块模式确定的候选块模式中执行运动估计多个块模式。

7. 发明申请

US20130272989A1 POLYSACCHARIDE-BASED GRAFT COPOLYMER AND COMPOSITION COMPRISING SAME FOR PERSONAL CARE 审中-公开
标题翻译：基于聚合物的共聚物和包含个人护理相同的组合物
公开(公告)号：US20130272989A1
公开(公告)日：2013-10-17
申请号：US13995475
申请日：2011-12-29
申请人： Mae In Lee , In Sun Han , Ho Jin Lee , Han Soo Kim
发明人： Mae In Lee , In Sun Han , Ho Jin Lee , Han Soo Kim
IPC分类号： A61K8/91 , A61Q19/00 , A61Q5/00
CPC分类号： A61K8/91 , A61K8/731 , A61Q5/00 , A61Q5/002 , A61Q19/00 , C08B11/02 , C08B11/08 , C08B31/00 , C08B37/0087 , C08B37/0093 , C08B37/0096 , C08F251/00 , C08G65/331 , C08G65/3314 , C08G65/333 , C08G65/3356 , C08L1/28 , C08L1/284 , C08L3/04 , C08L5/00 , C08L51/02 , C08F230/02
摘要： The present invention relates to a graft copolymer including a polysaccharide as a main chain and a phosphorylcholine analogous group-containing monomer as a side chain, and a composition for skin and hair care including the copolymer as an active ingredient. The graft copolymer according to the present invention exhibits more improved moisturizing capacity and better biocompatibility than the existing polysaccharide-based graft copolymer by introducing a phosphorylcholine analogous group-containing compound, and accordingly, the composition for hair and skin care including the same also has improved moisturizing capacity, protection capacity of damaged hair, skin affinity, a skin barrier function, and the like.
摘要翻译：本发明涉及包含多糖作为主链的接枝共聚物和作为侧链的磷酸胆碱类似基团的单体，以及包含该共聚物作为活性成分的皮肤和护发组合物。根据本发明的接枝共聚物通过引入含磷酸胆碱类似基团的化合物，显示出比现有的多糖类接枝共聚物更好的保湿能力和更好的生物相容性，因此包括它的头发和皮肤护理组合物也有改善保湿能力，受损毛发的保护能力，皮肤亲和力，皮肤屏障功能等。

8. 发明授权

US08559871B2 Dual mode satellite very small aperture terminal apparatus and controlling method thereof 有权
标题翻译：双模卫星非常小孔径终端设备及其控制方法
公开(公告)号：US08559871B2
公开(公告)日：2013-10-15
申请号：US12973517
申请日：2010-12-20
申请人： Pan Soo Kim , Jae Hee Han , Dae Ig Chang , Ho Jin Lee
发明人： Pan Soo Kim , Jae Hee Han , Dae Ig Chang , Ho Jin Lee
IPC分类号： H04B7/185
CPC分类号： H04B7/18528
摘要： Provided are a satellite VSAT apparatus and a control method thereof. The satellite VSAT apparatus according to an exemplary embodiment of the present invention can switch a modulation type of a signal to be transmitted from an indoor unit (IDU) to the outdoor unit to a linear or non-linear type in a case in which outputting of a transmitted signal is not controlled to an outdoor unit due to limitations, that is, there is no function such as an automatic signal level control in a block up-converter (BUC), a case in which transmission output limitation is large due to a lot of interference requirements for an adjacent channel, a case in which the number of adjacent channels (carriers) is large, or a case in which adjacent channel interference is large due to a frequency in a satellite multi-beam environment and polarization reuse, in a satellite VSAT apparatus system which aims at a low-priced user terminal.
摘要翻译：提供了一种卫星VSAT装置及其控制方法。在根据本发明的示例性实施例的卫星VSAT装置可以将输出从室内单元（IDU）到室外单元的信号的调制类型切换到线性或非线性类型，发送信号由于限制而不被控制到室外机，也就是说，在块升压转换器（BUC）中不存在诸如自动信号电平控制的功能，由于发送信号的发送输出限制大相邻信道的大量干扰要求，相邻信道（载波）数量大的情况，或由于卫星多波束环境中的频率和极化重用而导致相邻信道干扰较大的情况，在卫星VSAT装置系统，其目的在于低价格的用户终端。

9. 发明授权

US08482630B2 Apparatus and method for adjusting automatic white balance by detecting effective area 有权
标题翻译：通过检测有效面积来调节自动白平衡的装置和方法
公开(公告)号：US08482630B2
公开(公告)日：2013-07-09
申请号：US12858176
申请日：2010-08-17
申请人： Young Sun Jeon , Ho Jin Lee , Young Su Moon , Shi Hwa Lee
发明人： Young Sun Jeon , Ho Jin Lee , Young Su Moon , Shi Hwa Lee
IPC分类号： H04N9/73
CPC分类号： H04N9/735 , G06T5/007 , G06T7/11 , G06T2207/10024
摘要： An automatic white balance adjusting apparatus and method based on detection of an effective area. The automatic white balance adjusting apparatus may detect the effective area by using a color temperature, a luminance, and a correlation, and may adjust a white balance with respect to the detected effective area.
摘要翻译：一种基于检测有效面积的自动白平衡调节装置和方法。自动白平衡调节装置可以通过使用色温，亮度和相关性来检测有效面积，并且可以相对于检测到的有效面积调整白平衡。

10. 发明授权

US08422600B2 Apparatus and method for estimating phase error based on variable step size 有权
标题翻译：基于可变步长估计相位误差的装置和方法
公开(公告)号：US08422600B2
公开(公告)日：2013-04-16
申请号：US12536856
申请日：2009-08-06
申请人： Pansoo Kim , Dae-Ig Chang , Ho-Jin Lee , Jin-Young Kim , Jae-Sung Park , Young-Sun Lim
发明人： Pansoo Kim , Dae-Ig Chang , Ho-Jin Lee , Jin-Young Kim , Jae-Sung Park , Young-Sun Lim
IPC分类号： H04L27/06 , H03M13/03
CPC分类号： H04L27/22 , H04L1/0047 , H04L1/005 , H04L1/0066 , H04L2027/0067
摘要： Disclosed is a phase error estimating an apparatus and a method which provides improved convergence speed and tracking speed even in mobile channel environment by variably applying the step size for phase error estimation according to channel status. The apparatus for estimating a phase error includes: a posterior probability (APP) average calculating unit for calculating an APP average value from a soft decision result of a currently received symbol; a step size determining unit for determining a step size variably according to channel status; and a phase error estimating unit for estimating a phase error of the currently received symbol from a phase error of a previously received symbol and the APP average value by using the variably determined step size.
摘要翻译：公开了一种相位误差估计装置和方法，即使在移动信道环境中也可以通过根据信道状态可变地应用步长来进行相位误差估计，从而提高收敛速度和跟踪速度。用于估计相位误差的装置包括：后验概率（APP）平均计算单元，用于根据当前接收的符号的软判决结果计算APP平均值; 步长确定单元，用于根据信道状态可变地确定步长; 以及相位误差估计单元，用于通过使用可变确定的步长来估计来自先前接收到的符号的相位误差的当前接收到的符号的相位误差和APP平均值。

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