专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090032974A1 METHOD AND STRUCTURE TO REDUCE CRACKING IN FLIP CHIP UNDERFILL 有权
标题翻译：减少裂片碎屑破碎的方法和结构
公开(公告)号：US20090032974A1
公开(公告)日：2009-02-05
申请号：US11831026
申请日：2007-07-31
申请人： Mukta G. Farooq , Robert Hannon , Dae-Young Jung , Ian D. Melville
发明人： Mukta G. Farooq , Robert Hannon , Dae-Young Jung , Ian D. Melville
IPC分类号： H01L21/00 , H01L23/528
CPC分类号： H01L21/563 , H01L24/32 , H01L2224/05568 , H01L2224/05573 , H01L2224/131 , H01L2224/16225 , H01L2224/26145 , H01L2224/29036 , H01L2224/321 , H01L2224/32225 , H01L2224/73204 , H01L2224/831 , H01L2224/83379 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/13099 , H01L2224/05599
摘要： A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.
摘要翻译：组装微电子倒装芯片布置的方法包括将具有限定长度的芯片附接到支撑衬底，其中芯片在支撑衬底上形成具有限定长度的芯片阴影线，在外部形成第一非可湿润区域在芯片阴影线外部的支撑基板的一部分上形成第二不可润湿区域，在芯片上填充并形成圆角，其中圆角不延伸超过芯片阴影线，以及硬化底部填充物，包括圆角。

2. 发明申请

US20080274608A1 STRUCTURE AND METHOD FOR ENHANCING RESISTANCE TO FRACTURE OF BONDING PADS 有权
标题翻译：结构和方法提高结合力的破坏
公开(公告)号：US20080274608A1
公开(公告)日：2008-11-06
申请号：US12174074
申请日：2008-07-16
申请人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
发明人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
IPC分类号： H01L21/768
CPC分类号： H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/02351 , H01L2224/0401 , H01L2224/05073 , H01L2224/05094 , H01L2224/05095 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13006 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05599 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.
摘要翻译：本发明提供了半导体集成电路和芯片封装之间的接合焊盘结构，其具有增强的抗断裂性和改进的可靠性。在粘结结构中使用的材料之间的温度膨胀系数（CTE）的不匹配会对其造成应力和剪切，这可能导致后端介质堆叠中的断裂，并导致包装的可靠性问题。通过设置通过多个金属通孔连接到接合焊盘的多个金属焊盘，增强了接合焊盘和后端电介质叠层之间的粘附力。

3. 发明申请

US20080111250A1 STRUCTURE AND METHOD FOR ENHANCING RESISTANCE TO FRACTURE OF BONDING PADS 有权
公开(公告)号：US20080111250A1
公开(公告)日：2008-05-15
申请号：US11559130
申请日：2006-11-13
申请人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
发明人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/02351 , H01L2224/0401 , H01L2224/05073 , H01L2224/05094 , H01L2224/05095 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13006 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05599 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.

4. 发明授权

US07573115B2 Structure and method for enhancing resistance to fracture of bonding pads 有权
$Structure and method for enhancing resistance to fracture of bonding pads$
标题翻译：提高接合焊盘断裂性的结构和方法
公开(公告)号：US07573115B2
公开(公告)日：2009-08-11
申请号：US11559130
申请日：2006-11-13
申请人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
发明人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
IPC分类号： H01L23/52
CPC分类号： H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/02351 , H01L2224/0401 , H01L2224/05073 , H01L2224/05094 , H01L2224/05095 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13006 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05599 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.
摘要翻译：本发明提供了半导体集成电路和芯片封装之间的接合焊盘结构，其具有增强的抗断裂性和改进的可靠性。在粘结结构中使用的材料之间的温度膨胀系数（CTE）的不匹配会对其造成应力和剪切，这可能导致后端介质堆叠中的断裂，并导致包装的可靠性问题。通过设置通过多个金属通孔连接到接合焊盘的多个金属焊盘，增强了接合焊盘和后端电介质叠层之间的粘附力。

5. 发明授权

US07919356B2 Method and structure to reduce cracking in flip chip underfill 有权
标题翻译：倒装芯片底部填充物的开裂方法和结构
公开(公告)号：US07919356B2
公开(公告)日：2011-04-05
申请号：US11831026
申请日：2007-07-31
申请人： Mukta G. Farooq , Robert Hannon , Dae-Young Jung , Ian D. Melville
发明人： Mukta G. Farooq , Robert Hannon , Dae-Young Jung , Ian D. Melville
IPC分类号： H01L21/44
CPC分类号： H01L21/563 , H01L24/32 , H01L2224/05568 , H01L2224/05573 , H01L2224/131 , H01L2224/16225 , H01L2224/26145 , H01L2224/29036 , H01L2224/321 , H01L2224/32225 , H01L2224/73204 , H01L2224/831 , H01L2224/83379 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/13099 , H01L2224/05599
摘要： A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.
摘要翻译：组装微电子倒装芯片布置的方法包括将具有限定长度的芯片附接到支撑衬底，其中芯片在支撑衬底上形成具有限定长度的芯片阴影线，在外部形成第一非可湿润区域在芯片阴影线外部的支撑基板的一部分上形成第二不可润湿区域，在芯片上填充并形成圆角，其中圆角不延伸超过芯片阴影线，以及硬化底部填充物，包括圆角。

6. 发明授权

US07648891B2 Semiconductor chip shape alteration 失效
标题翻译：半导体芯片形状改变
公开(公告)号：US07648891B2
公开(公告)日：2010-01-19
申请号：US11615236
申请日：2006-12-22
申请人： Mukta G. Farooq , Dae-Young Jung , Ian D. Melville
发明人： Mukta G. Farooq , Dae-Young Jung , Ian D. Melville
IPC分类号： H01L21/78
CPC分类号： H01L21/67092 , H01L21/78 , H01L23/562 , H01L29/0657 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.
摘要翻译：本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。一旦从半导体晶片切割，半导体芯片就不会产生90度角角。

7. 发明申请

US20100019354A1 SEMICONDUCTOR CHIP SHAPE ALTERATION 审中-公开
标题翻译：半导体芯片形状改变
公开(公告)号：US20100019354A1
公开(公告)日：2010-01-28
申请号：US12573364
申请日：2009-10-05
申请人： Mukta G. Farooq , Dae-Young Jung , Ian D. Melville
发明人： Mukta G. Farooq , Dae-Young Jung , Ian D. Melville
IPC分类号： H01L23/58 , H01L23/544
CPC分类号： H01L21/67092 , H01L21/78 , H01L23/562 , H01L29/0657 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.
摘要翻译：本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。一旦从半导体晶片切割，半导体芯片就不会产生90度角角。

8. 发明申请

US20080029898A1 VIA STACK STRUCTURES 审中-公开
标题翻译：通过堆叠结构
公开(公告)号：US20080029898A1
公开(公告)日：2008-02-07
申请号：US11461511
申请日：2006-08-01
申请人： Mukta G. Farooq , Robert Hannon , Dae Young Jung , Ian D. Melville , Donna S. Zupanski-Nielsen
发明人： Mukta G. Farooq , Robert Hannon , Dae Young Jung , Ian D. Melville , Donna S. Zupanski-Nielsen
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Via stack structures are disclosed. In one embodiment, a structure includes a via stack including: a first substantially cross-shaped line in a first dielectric layer; a second substantially cross-shaped line set in a second dielectric layer, and a via stud coupling the first substantially cross-shaped line to the second substantially cross-shaped line. In another embodiment, a structure includes a first via stack, and a second via stack, wherein the first via stack and the second via stack extend in a divergent manner from one another. Each via stack structure is useful for support, for example, in under wire bond applications. The via stack structures can be mixed with other via stack structures and selectively placed within a layout to replace conventional metal plate and via stud array configurations.
摘要翻译：公开了通过堆叠结构。在一个实施例中，结构包括通孔堆叠，其包括：第一介电层中的第一基本十字形的线; 设置在第二电介质层中的第二基本上十字形的线，以及将第一基本上十字形的线耦合到第二基本十字形线的通孔柱。在另一个实施例中，结构包括第一通孔堆叠和第二通孔堆叠，其中第一通孔堆叠和第二通孔堆叠以彼此发散的方式延伸。每个通孔堆叠结构可用于支持，例如在引线键合应用中。通孔堆叠结构可以与其它通孔堆叠结构混合并且选择性地放置在布局内以代替传统的金属板和经由螺柱阵列配置。

9. 发明授权

US07867887B2 Structure and method for enhancing resistance to fracture of bonding pads 有权
$Structure and method for enhancing resistance to fracture of bonding pads$
标题翻译：提高接合焊盘断裂性的结构和方法
公开(公告)号：US07867887B2
公开(公告)日：2011-01-11
申请号：US12174074
申请日：2008-07-16
申请人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
发明人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
IPC分类号： H01L21/768
CPC分类号： H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/02351 , H01L2224/0401 , H01L2224/05073 , H01L2224/05094 , H01L2224/05095 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13006 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05599 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.
摘要翻译：本发明提供了半导体集成电路和芯片封装之间的接合焊盘结构，其具有增强的抗断裂性和改进的可靠性。在粘结结构中使用的材料之间的温度膨胀系数（CTE）的不匹配会对其造成应力和剪切，这可能导致后端介质堆叠中的断裂，并导致包装的可靠性问题。通过设置通过多个金属通孔连接到接合焊盘的多个金属焊盘，增强了接合焊盘和后端电介质叠层之间的粘附力。

10. 发明申请

US20080150087A1 SEMICONDUCTOR CHIP SHAPE ALTERATION 失效
标题翻译：半导体芯片形状改变
公开(公告)号：US20080150087A1
公开(公告)日：2008-06-26
申请号：US11615236
申请日：2006-12-22
申请人： Mukta G. Farooq , Dae-Young Jung , Ian D. Melville
发明人： Mukta G. Farooq , Dae-Young Jung , Ian D. Melville
IPC分类号： H01L23/544 , H01L21/00
CPC分类号： H01L21/67092 , H01L21/78 , H01L23/562 , H01L29/0657 , H01L2924/0002 , H01L2924/00
摘要： The invention is directed to an improved semiconductor chip that reduces crack initiation and propagation into the active area of a semiconductor chip. A semiconductor wafer includes dicing channels that separate semiconductor chips and holes through a portion of a semiconductor chip, which are located at the intersection of the dicing channels. Once diced from the semiconductor wafer, semiconductor chips are created without ninety degree angle corners.
摘要翻译：本发明涉及一种改进的半导体芯片，其减少裂纹发生和传播到半导体芯片的有源区域。半导体晶片包括分开半导体芯片和穿过半导体芯片的位于切割通道的交叉点的部分的切割通道。一旦从半导体晶片切割，半导体芯片就不会产生90度角角。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式