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    • 8. 发明授权
    • Method and system of implementing an early data dependency resolution
mechanism in a high-performance data processing system utilizing
out-of-order instruction issue
    • 在采用无序指令问题的高性能数据处理系统中实现早期数据依赖解析机制的方法和系统
    • US5812812A
    • 1998-09-22
    • US740911
    • 1996-11-04
    • Muhammad Nural AfsarRomesh Mangho JessaniSoummya MallickRobert Greg McDonaldMukesh Sharma
    • Muhammad Nural AfsarRomesh Mangho JessaniSoummya MallickRobert Greg McDonaldMukesh Sharma
    • G06F9/38
    • G06F9/3838G06F9/3836G06F9/384
    • A method and system of implementing an early data dependency resolution mechanism for a high-performance data processing system that utilizes out-of-order instruction issue is disclosed. In accordance with the present disclosure, an instruction cache and a register-dependency cache are provided. The instruction cache has multiple cache lines, and each of these cache lines is capable of storing multiple instructions. The register-dependency cache contains an identical number of cache lines as in the instruction cache, and each of the cache lines within the register-dependency cache is capable of storing an identical number of register-dependency units as instructions in each of the cache lines within the instruction cache. In a single processor cycle, a group of register-dependency units are fetched from the register-dependency cache. All register-dependency units that have no forward data dependency within the group of register-dependency units are identified utilizing an Instruction Dispatch Unit. Each of the identified register-dependency units is then translated to its respective instruction utilizing a corresponding cache line within the instruction cache. All of the translated instructions are issued within a next processor cycle.
    • 公开了一种利用无序指令问题的高性能数据处理系统实现早期数据依赖解析机制的方法和系统。 根据本公开,提供了指令高速缓存和寄存器依赖性高速缓存。 指令高速缓存具有多个高速缓存行,并且这些高速缓存行中的每一条都能够存储多个指令。 寄存器依赖性高速缓存包含与指令高速缓存中相同数量的高速缓存行,并且寄存器相关高速缓存内的每个高速缓存线能够存储与每个高速缓存行中的指令相同数量的寄存器依赖单元 在指令缓存中。 在单个处理器周期中,从寄存器依赖性缓存中取出一组寄存器依赖单元。 使用指令调度单元来识别在寄存器依赖单元组内没有转发数据依赖性的所有寄存器依赖单元。 然后,使用所述指令高速缓存中的相应高速缓存行,将所识别的寄存器依赖单元中的每一个转换为其相应的指令。 所有翻译的指令都是在下一个处理器周期内发出的。