专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5999743A System and method for dynamically allocating accelerated graphics port memory space 失效
标题翻译：用于动态分配加速图形端口存储空间的系统和方法
公开(公告)号：US5999743A
公开(公告)日：1999-12-07
申请号：US926422
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliot
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliot
IPC分类号： G06F3/14 , G09G5/36 , G09G5/39 , B06F13/00
CPC分类号： G06F3/14 , G09G5/363 , G09G2360/121
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址启动或POST。

2. 发明授权

US5949436A Accelerated graphics port multiple entry gart cache allocation system and method 失效
标题翻译：加速图形端口多进入gart缓存分配系统和方法
公开(公告)号：US5949436A
公开(公告)日：1999-09-07
申请号：US941861
申请日：1997-09-30
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
IPC分类号： G06F12/10 , G06T1/60 , G06F15/00 , G06T1/00
CPC分类号： G06T1/60 , G06F12/1027 , G06F12/1081
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. When a GART table entry is not found in the cache, a memory access is required to obtained the needed GART table entry. There are two GART table entries in each quadword returned in toggle mode of the cacheline of memory information returned from the memory read access. At least one quadword (two GART table entries) are stored in the cache each time a memory access is required because of a cache miss.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）由核心逻辑芯片组使用，将AGP图形控制器使用的虚拟内存地址重新映射到驻留在计算机系统内存中的物理内存地址GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际使用不连续的块或物理系统存储器的页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针。核心逻辑芯片组可以缓存最近使用的GART表项的子集，以在执行地址转换时提高AGP性能。当缓存中没有找到GART表条目时，需要内存访问才能获取所需的GART表条目。在内存读取访问返回的内存信息的缓存行的切换模式下，每个四字中有两个GART表条目。由于缓存未命中，每次需要存储器访问时，至少有一个四字（两个GART表条目）存储在缓存中。

3. 发明授权

US5990914A Generating an error signal when accessing an invalid memory page 失效
标题翻译：访问无效内存页面时产生错误信号
公开(公告)号：US5990914A
公开(公告)日：1999-11-23
申请号：US926425
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F11/07 , G06F13/16
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0745 , G06F3/14
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page. When the feature flag Present Bit is set, the memory page has been reserved in the physical memory for graphics data and an address translation may be carried out. When the feature flag Present Bit is clear, the memory page has not been reserved for graphics data in the physical memory and a determination must then be made whether to perform the translation or generate an error signal to the computer processor.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。其中一个功能标志用作相应存储器页面的当前位。当特征标志当前位被设置时，存储器页面已被保留在用于图形数据的物理存储器中，并且可以执行地址转换。当特征标志当前位清除时，存储器页面尚未被保留用于物理存储器中的图形数据，然后必须确定是否执行转换或者向计算机处理器生成错误信号。

4. 发明授权

US5936640A Accelerated graphics port memory mapped status and control registers 失效
标题翻译：加速图形端口存储器映射状态和控制寄存器
公开(公告)号：US5936640A
公开(公告)日：1999-08-10
申请号：US941862
申请日：1997-09-30
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F12/10 , G06F15/00 , G06F12/06
CPC分类号： G06F3/14 , G06F12/1027 , G06F12/1081
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。多个AGP存储器映射状态和控制寄存器存储在计算机系统存储器中，用于计算机系统中AGP功能的状态和控制。

5. 发明授权

US5914727A Valid flag for disabling allocation of accelerated graphics port memory space 失效
标题翻译：禁止分配加速图形端口内存空间的有效标志
公开(公告)号：US5914727A
公开(公告)日：1999-06-22
申请号：US925773
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F12/02 , G06F12/10 , H04N7/26 , H04N7/50 , G06F15/16
CPC分类号： G06F12/1081 , G06F12/0292 , H04N19/423 , H04N19/61
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not. If the AGP device is not present, then no virtual memory address space is allocated during the computer system startup.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址启动或POST。 AGP有效位设置为指示AGP设备是否存在。如果AGP设备不存在，则在计算机系统启动期间不会分配虚拟内存地址空间。

6. 发明授权

US6078338A Accelerated graphics port programmable memory access arbiter 失效
标题翻译：加速图形端口可编程存储器访问仲裁器
公开(公告)号：US6078338A
公开(公告)日：2000-06-20
申请号：US38412
申请日：1998-03-11
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Gary J. Piccirillo
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Gary J. Piccirillo
IPC分类号： G06F3/14 , G06F13/16 , G09G1/16 , G09G5/00 , G09G5/36
CPC分类号： G06F13/1605 , G06F3/14 , G09G3/003 , G09G5/001 , G09G5/363
摘要： A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.
摘要翻译：具有将处理器，系统存储器和外围设备代理器互连的核心逻辑芯片组的计算机系统。核心逻辑芯片组具有可编程存储器访问仲裁器，其可以被编程为优化计算机系统处理器和代理到系统存储器的访问以获得最佳计算机系统性能。存储器访问仲裁器可以针对每个系统代理进行编程。访问计数寄存器可以并入到核心逻辑芯片组中，其中每个系统代理可以由访问计数寄存器的一部分来表示。编程到访问计数寄存器的部分中的值确定在授予存储器访问的另一个代理程序之前，相关联的代理可以执行多少内存访问，以及在存储器访问期间可以传送多少个高速缓存行。

7. 发明授权

US5999198A Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device 失效
标题翻译：图形地址重映射表条目功能标志，用于自定义与加速图形端口设备关联的内存页面的操作
公开(公告)号：US5999198A
公开(公告)日：1999-12-07
申请号：US925772
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F12/08 , G09G5/393 , G06F15/16
CPC分类号： G06F3/14 , G06F12/0875 , G09G5/393 , G09G2360/121
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器页面的基址的地址指针，以及可用于定制关联的存储器页面的特征标志。

8. 发明授权

US5986677A Accelerated graphics port read transaction merging 失效
标题翻译：加速图形端口读取事务合并
公开(公告)号：US5986677A
公开(公告)日：1999-11-16
申请号：US941859
申请日：1997-09-30
申请人： Phillip M. Jones , Ronald T. Horan , Gregory N. Santos
发明人： Phillip M. Jones , Ronald T. Horan , Gregory N. Santos
IPC分类号： G06F13/16 , G06F13/14
CPC分类号： G06F13/1631
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as an AGP graphics controller, and a host processor and computer system memory wherein AGP transaction read requests are merged from the AGP graphics controller and retired when these requests are within a cacheline of the memory being accessed. The core logic chipset will request a memory cacheline read as it begins processing a current AGP transaction read request. Once the memory read access is initiated, the transaction read request will be popped off an AGP request queue in order to evaluate the next in order transaction request. If the next request can be partially or completely retired by the memory read access previously started, then the memory access that would have been normally required may be skipped and the data from the previous memory read access is used instead. This AGP read transaction merging may continue until the next in order transaction read request is located in a different cacheline of memory or the original memory request is ready to return data. A memory data buffer may also be utilized to store unused quadwords of the cacheline read from a memory access so that some subsequent AGP transaction requests may be retired without having to access a previously read cacheline of memory.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为AGP图形控制器之间的加速图形端口（“AGP”）总线装置与主机处理器之间的桥接，以及AGP事务读取请求从AGP合并的计算机系统存储器图形控制器，并且当这些请求在被访问的存储器的高速缓存行内时退出。核心逻辑芯片组将在开始处理当前的AGP事务读取请求时请求存储器高速缓存行读取。一旦启动了存储器读取访问，事务读取请求将从AGP请求队列中弹出，以便按顺序对事务请求进行评估。如果下一个请求可以被先前启动的存储器读取访问部分地或完全地退出，则可以跳过通常需要的存储器访问，而是使用来自先前的存储器读取访问的数据。该AGP读取事务合并可以继续，直到顺序事务读取请求位于存储器的不同高速缓存行中，或者原始存储器请求准备好返回数据。存储器数据缓冲器还可以用于存储从存储器访问读取的高速缓存行的未使用的四字，使得一些后续的AGP事务请求可以被停止，而不必访问先前读取的存储器的高速缓存行。

9. 发明授权

US5761460A Reconfigurable dual master IDE interface 失效
标题翻译：可重新配置双主IDE接口
公开(公告)号：US5761460A
公开(公告)日：1998-06-02
申请号：US684490
申请日：1996-07-19
申请人： Gregory N. Santos , David J. Maguire , William C. Hallowell , James R. Edwards
发明人： Gregory N. Santos , David J. Maguire , William C. Hallowell , James R. Edwards
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/385
摘要： A dual-master data storage interface is disclosed which flexibly configures and connects data storage drives in the portable computer to optimize performance when the portable computer is operating in a stand-alone mode and to optimize accessibility to additional data storage drives when the portable computer is docked with an expansion unit. When the portable computer operates as a stand-alone unit (i.e., not docked to the expansion unit), each drive on the portable is configured to operate as a master drive to optimize performance. When the portable computer docks with the expansion unit, the first channel on the portable computer is connected via switches to both drives of the portable computer, while the second channel on the portable computer is disconnected. Further, the first data storage drive is configured as a master and the second data storage drive is configured as a slave drive on the portable computer side. Correspondingly, the drives located on the expansion base unit are reconfigured and remapped as master and slave drives on the second channel on the expansion base unit, while the first channel on the expansion base unit is disconnected.
摘要翻译：公开了一种双主数据存储接口，其灵活地配置和连接便携式计算机中的数据存储驱动器，以便当便携式计算机以独立模式操作时优化性能，并且当便携式计算机是与扩展单元对接。当便携式计算机作为独立单元（即，未对准扩展单元）运行时，便携式计算机上的每个驱动器被配置为作为主驱动器来操作以优化性能。当便携式计算机与扩展单元对接时，便携式计算机上的第一通道通过开关连接到便携式计算机的两个驱动器，而便携式计算机上的第二通道断开连接。此外，第一数据存储驱动器被配置为主机，并且第二数据存储驱动器被配置为便携式计算机侧的从驱动器。相应地，位于扩展基座单元上的驱动器在扩展基板单元上的第二通道上被重新配置和重新映射为主从驱动器，而扩展基板上的第一通道被断开。

10. 发明授权

US5522050A Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus 失效
标题翻译：用于多总线信息处理系统的总线到总线桥，可优化系统总线和外设总线之间的数据传输
公开(公告)号：US5522050A
公开(公告)日：1996-05-28
申请号：US68877
申请日：1993-05-28
申请人： Nader Amini , Ashu Kohli , Gregory N. Santos
发明人： Nader Amini , Ashu Kohli , Gregory N. Santos
IPC分类号： G06F13/36 , G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4027 , G06F13/28
摘要： Hardware logic within a host bridge that connects a system bus to a peripheral bus using PCI bus architecture or a peripheral bus that uses a bus architecture similar to PCI. The hardware optimizes the speed at which data transfers are accomplished between the buses while translating the data transfers between the different architectures of the two buses.
摘要翻译：使用PCI总线架构或使用类似于PCI的总线架构的外设总线将系统总线连接到外设总线的主机桥内的硬件逻辑。硬件优化在总线之间完成数据传输的速度，同时在两条总线的不同架构之间转换数据传输。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式