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1. 发明授权

US07707568B2 Compiler optimization 失效
标题翻译：编译器优化
公开(公告)号：US07707568B2
公开(公告)日：2010-04-27
申请号：US11133897
申请日：2005-05-20
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： An optimization method that optimizes programs is disclosed. A pattern for multiple instructions is used to replace one of a plurality of partial programs with a replacement set of instructions. The partial program to be optimized is detected within a first set of instructions. The first set of instructions is transformed in the one of the plurality of partial programs and is replaced with the replacement set of instructions.
摘要翻译：公开了优化程序的优化方法。用于多个指令的模式用于用替换指令集来替换多个部分程序中的一个。要在第一组指令内检测要优化的部分程序。第一组指令被变换为多个部分程序中的一个，并被替换的指令集替换。

2. 发明授权

US06944852B2 Compiler 失效
标题翻译：编译器
公开(公告)号：US06944852B2
公开(公告)日：2005-09-13
申请号：US09828402
申请日：2001-04-06
申请人： Akira Koseki , Hiroyuki Momose , Motohiro Kawahito , Hideaki Komatsu
发明人： Akira Koseki , Hiroyuki Momose , Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45 , G08F9/45
CPC分类号： G06F8/443
摘要： A compiler is provided which effectively performs a data flow optimization process for a program wherein a plurality of branches and merges are arranged in series, without incurring a drastic increase in the amount of code. The compiler, and the method thereof, may be implemented in hardware, software, or both.
摘要翻译：提供了一种编译器，其有效地执行用于其中多个分支和合并被串联布置的程序的数据流优化过程，而不会导致代码量的急剧增加。编译器及其方法可以在硬件，软件或两者中实现。

3. 发明授权

US06665864B1 Method and apparatus for generating code for array range check and method and apparatus for versioning 有权
标题翻译：用于生成阵列范围检查代码的方法和装置以及用于版本控制的方法和装置
公开(公告)号：US06665864B1
公开(公告)日：2003-12-16
申请号：US09473858
申请日：1999-12-28
申请人： Motohiro Kawahito , Hideaki Komatsu , Toshiaki Yasue
发明人： Motohiro Kawahito , Hideaki Komatsu , Toshiaki Yasue
IPC分类号： G06F945
CPC分类号： G06F8/443
摘要： The present invention eliminates redundant array range checks. A two-phased check is performed, namely a wide range check is performed by combining a plurality of array range checks, and a strict range check is unsuccessful, so as to reduce the number of range checks at execution time and allow execution at high speed. For instance, it is possible with a processor such as PowerPC, by using a flag, to invalidate a code for performing an array range check at high speed without increasing a code size. Consequently, the number of array range checks to be executed can be reduced so as to allow execution at high speed. Also, for instance, a plurality of array range checks can be combined without considering existence of instructions which cause a side effect. Consequently, the number of array range checks to be executed can be reduced so as to allow execution at high speed. In addition, a versioning is performed by using, as array access information for versioning, information of array access information for versioning information of array accesses which are always performed even if passing through any execution path in a loop so that there are fewer cases where it goes to a version with a larger number of array range checks at execution time.
摘要翻译：本发明消除了冗余阵列范围检查。执行两阶段检查，即通过组合多个阵列范围检查来进行宽范围检查，并且严格范围检查不成功，以便在执行时减少范围检查的数量并允许高速执行。例如，通过使用标志，诸如PowerPC的处理器可以在不增加代码大小的情况下使用于高速执行阵列范围检查的代码无效。因此，可以减少要执行的阵列范围检查的数量，以便允许高速执行。此外，例如，可以组合多个阵列范围检查，而不考虑存在导致副作用的指令。因此，可以减少要执行的阵列范围检查的数量，以便允许高速执行。另外，通过使用用作版本控制的数组访问信息来执行版本控制，即使通过循环中的任何执行路径也始终执行的阵列访问的版本控制信息的数组访问信息的信息，从而存在更少的情况在执行时转到具有更大数量的数组范围检查的版本。

4. 发明授权

US07383544B2 Compiler device, method, program and recording medium 失效
标题翻译：编译器装置，方法，程序和记录介质
公开(公告)号：US07383544B2
公开(公告)日：2008-06-03
申请号：US10793370
申请日：2004-03-04
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in a first instruction sequence and a second instruction included in a second instruction sequence executed after the first instruction sequence can be replaced with a common processing instruction group including a common processing instruction for processing at least respective parts of processings by the first and second instructions together; a common processing instruction group generation unit which generates a common processing instruction group in the first instruction sequence, in place of the first instruction, when the replaceability determination unit determines the first and second instructions to be replaceable; and an instruction insertion unit which inserts the second instruction into a third instruction sequence that is an instruction sequence other than the first instruction sequence and is executed before the second instruction sequence.
摘要翻译：编译器设备通过更改执行指令的顺序来优化程序。该装置包括：可替换性确定单元，其确定包括在第一指令序列中的第一指令和包括在第一指令序列之后执行的第二指令序列中的第二指令是否可以被包括公共处理指令的公共处理指令组替换用于通过第一和第二指令一起处理至少相应的处理部分; 当可替换性确定单元确定可替换的第一和第二指令时，代替第一指令，生成第一指令序列中的公共处理指令组的公共处理指令组生成单元; 以及指令插入单元，其将第二指令插入作为第一指令序列以外的指令序列的第三指令序列，并且在第二指令序列之前执行。

5. 发明申请

US20050268293A1 Compiler optimization 失效
标题翻译：编译器优化
公开(公告)号：US20050268293A1
公开(公告)日：2005-12-01
申请号：US11133897
申请日：2005-05-20
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： Provides effective use of architecture-specific instructions. There is provided a compiler including: a target partial program detecting unit for detecting, from among a partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced as a partial program to be optimized; an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced, so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced; an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with a target instruction sequence determined in accordance with the pattern to be replaced.
摘要翻译：提供针对特定于架构的指令的有效使用。提供了一种编译器，其包括：目标部分程序检测单元，用于从要优化的程序的部分程序中检测包括与要替换的模式中包括的所有指令相对应的指令作为部分程序的部分程序，优化; 指令序列变换单元，用于在要优化的部分程序中转换除了与要替换的模式中包括的指令相对应的指令以及具有与要替换的模式不同的执行依赖性的指令之外的指令，使得指令之间的依赖性包括在要优化的部分程序中匹配待更换的模式; 指令序列替换单元，用于将由指令序列变换单元变换的要优化的部分程序替换为根据要替换的模式确定的目标指令序列。

6. 发明申请

US20090007086A1 Compiler Optimization 审中-公开
标题翻译：编译器优化
公开(公告)号：US20090007086A1
公开(公告)日：2009-01-01
申请号：US12167421
申请日：2008-07-03
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： Provides effective use of architecture-specific instructions. There is provided a compiler including: a target partial program detecting unit for detecting, from among a partial programs of the program to be optimized, a partial program including instructions corresponding to all instructions included in the pattern to be replaced as a partial program to be optimized; an instruction sequence transforming unit for transforming, in the partial program to be optimized, instructions other than those instructions corresponding to instructions included in the pattern to be replaced and those instructions having execution dependencies different from the pattern to be replaced, so that dependencies between instructions included in the partial program to be optimized match the pattern to be replaced; an instruction sequence replacing unit for replacing the partial program to be optimized transformed by the instruction sequence transforming unit with a target instruction sequence determined in accordance with the pattern to be replaced.
摘要翻译：提供针对特定于架构的指令的有效使用。提供了一种编译器，其包括：目标部分程序检测单元，用于从要优化的程序的部分程序中检测包括与要替换的模式中包括的所有指令相对应的指令作为部分程序的部分程序，优化; 指令序列变换单元，用于在要优化的部分程序中转换除了与要替换的模式中包括的指令相对应的指令以及具有与要替换的模式不同的执行依赖性的指令之外的指令，使得指令之间的依赖性包括在要优化的部分程序中匹配待更换的模式; 指令序列替换单元，用于将由指令序列变换单元变换的要优化的部分程序替换为根据要替换的模式确定的目标指令序列。

7. 发明授权

US06519765B1 Method and apparatus for eliminating redundant array range checks in a compiler 失效
标题翻译：用于在编译器中消除冗余阵列范围检查的方法和装置
公开(公告)号：US06519765B1
公开(公告)日：2003-02-11
申请号：US09350242
申请日：1999-07-09
申请人： Motohiro Kawahito , Toshiaki Yasue , Hideaki Komatsu
发明人： Motohiro Kawahito , Toshiaki Yasue , Hideaki Komatsu
IPC分类号： G06F944
CPC分类号： G06F8/43 , G06F8/443
摘要： Java language is, as its specification, capable of detecting an access exceeding an array range, and when there is no user-defined exception handler, moving control to an invoked method after getting out of a method in which an exception occurred, or when there is a user-defined exception handler, moving the process to the exception handler. Accordingly, an array range check is essential since occurrence of an exception may be described as a correct operation. However, an array range check slows execution speed compared with a language which does not require it. In an actual program, there is an array access to ensure that there is no access exceeding a range, and thus elimination of such redundant range checks greatly contributes to improved performance, and in addition, brings about an effect of expanding the range of optimization from the viewpoint of ensuring order of execution between occurrence of an exception and a process with a side effect such as an assignment of a value to an array.
摘要翻译： Java语言正如其规范那样能够检测到超出数组范围的访问，当没有用户定义的异常处理程序时，在得到发生异常的方法之后将控制移动到被调用的方法，或者在那里是一个用户定义的异常处理程序，将进程移动到异常处理程序。因此，阵列范围检查是重要的，因为异常的发生可以被描述为正确的操作。但是，与不需要的语言相比，数组范围检查会降低执行速度。在一个实际的程序中，有一个阵列访问，以确保没有超出范围的访问，因此消除这种冗余范围检查大大有助于提高性能，另外还带来了扩大优化范围的效果确保异常发生之间的执行顺序与具有副作用（例如将值分配给数组）的处理的观点。

8. 发明授权

US07979853B2 Compiler device, method, program and recording medium 失效
标题翻译：编译器装置，方法，程序和记录介质
公开(公告)号：US07979853B2
公开(公告)日：2011-07-12
申请号：US12019446
申请日：2008-01-24
申请人： Motohiro Kawahito , Hideaki Komatsu
发明人： Motohiro Kawahito , Hideaki Komatsu
IPC分类号： G06F9/45
CPC分类号： G06F8/41
摘要： Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in a first instruction sequence and a second instruction included in a second instruction sequence executed after the first instruction sequence can be replaced with a common processing instruction group including a common processing instruction for processing at least respective parts of processings by the first and second instructions together; a common processing instruction group generation unit which generates a common processing instruction group in the first instruction sequence, in place of the first instruction, when the replaceability determination unit determines the first and second instructions to be replaceable; and an instruction insertion unit which inserts the second instruction into a third instruction sequence that is an instruction sequence other than the first instruction sequence and is executed before the second instruction sequence.
摘要翻译：编译器设备通过更改执行指令的顺序来优化程序。该装置包括：可替换性确定单元，其确定包括在第一指令序列中的第一指令和包括在第一指令序列之后执行的第二指令序列中的第二指令是否可以被包括公共处理指令的公共处理指令组替换用于通过第一和第二指令一起处理至少相应的处理部分; 当可替换性确定单元确定可替换的第一和第二指令时，代替第一指令，生成第一指令序列中的公共处理指令组的公共处理指令组生成单元; 以及指令插入单元，其将第二指令插入作为第一指令序列以外的指令序列的第三指令序列，并且在第二指令序列之前执行。

9. 发明授权

US07950005B2 Method and apparatus for performing versioning for loop, method and apparatus for collecting array range check information in basic blocks, method for modifying array range check information, method for optimizing array range checks, method for generating codes for array range checks, method and apparatus for eliminating redundant array range checks, method for selecting array range checks, method for modifying array range checks, method for collecting array range checks, and method for determining handling of array range checks 失效
标题翻译：用于执行循环的方法和装置，用于收集基本块中的阵列范围检查信息的方法和装置，用于修改阵列范围检查信息的方法，用于优化阵列范围检查的方法，用于生成阵列范围检查的代码的方法，方法和装置消除冗余阵列范围检查，选择阵列范围检查的方法，修改阵列范围检查的方法，采集数组范围检查的方法以及确定数组范围检查处理的方法
公开(公告)号：US07950005B2
公开(公告)日：2011-05-24
申请号：US11838734
申请日：2007-08-14
申请人： Motohiro Kawahito , Toshiaki Yasue , Hideaki Komatsu
发明人： Motohiro Kawahito , Toshiaki Yasue , Hideaki Komatsu
IPC分类号： G06F9/44
CPC分类号： G06F8/437 , G06F8/4441
摘要： A system and method are provided that in one aspect eliminate redundant array range checks by performing a versioning for a loop. In another aspect, a system and method optimize array range checks by performing data-flow analysis in reverse order of the program execution. Yet in another aspect, a system and method obtains information about array ranges already checked by performing data-flow analysis in program execution order and eliminate redundant array range checks from this information.
摘要翻译：提供了一种系统和方法，其一方面通过执行循环的版本控制来消除冗余阵列范围检查。在另一方面，系统和方法通过以与程序执行相反的顺序执行数据流分析来优化阵列范围检查。另一方面，系统和方法通过以程序执行顺序执行数据流分析获得已经检查的数组范围的信息，并从该信息中消除冗余阵列范围检查。

10. 发明申请

US20090119654A1 COMPILER FOR OPTIMIZING PROGRAM 失效
标题翻译：编译器优化程序
公开(公告)号：US20090119654A1
公开(公告)日：2009-05-07
申请号：US12259746
申请日：2008-10-28
申请人： Motohiro Kawahito , Hideaki Komatsu , Takao Moriyama
发明人： Motohiro Kawahito , Hideaki Komatsu , Takao Moriyama
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F8/4435
摘要： A compiler system and method for calculating a value to be assigned to a variable for optimizing a program. The apparatus includes a subrange analysis unit for analyzing, for an instruction to assign a value to a variable in the program, a range of the value being assignable to the variable by the instruction, as a subrange of the variable in a case where instruction is executed; a determination unit for determining if the execution result of the program changes if the instruction assigns any value in the subrange of the variable to the variable on the basis of the analyzed subrange of the variable; and a replacement unit for replacing the instruction to assign the value to the variable with an instruction to assign a constant value in the subrange of the variable to the variable.
摘要翻译：用于计算要分配给用于优化程序的变量的值的编译器系统和方法。该装置包括一个子范围分析单元，用于对于在程序中的变量分配值的指令，分析指令中可变量值的范围，作为在指令为执行确定单元，用于如果所述指令基于所分析的所述变量的子范围将所述变量的子范围中的任何值分配给所述变量，则确定所述程序的执行结果是否改变; 以及替换单元，用于用指令将变量的子范围中的常数值分配给变量来替换指定给变量的指令。

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