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1. 发明申请

US20020094697A1 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same 有权
标题翻译：具有部分地在腔中制造的电容器结构的DRAM单元及其操作方法
公开(公告)号：US20020094697A1
公开(公告)日：2002-07-18
申请号：US10033690
申请日：2001-11-02
申请人： Monolithic System Technology, Inc.
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L021/31
CPC分类号： H01L27/1085 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.
摘要翻译：一种包括动态随机存取存储器（DRAM）单元的存储器系统，其包括存储晶体管和在半导体衬底中制造的电容器结构。电容器结构通过在浅沟槽隔离区域中形成空腔来制造，从而将衬底的侧壁区域暴露在衬底的上表面下方。在衬底的上表面和侧壁区域上形成介电层。在电介质层之上形成多晶硅层并构图以形成在衬底的上表面和侧壁区域上延伸的电容器结构的电容器电极。电容器电极部分地凹入到衬底的上表面之下。多晶硅层也被图案化以形成存取晶体管的栅电极。

2. 发明申请

US20040260983A1 Latched sense amplifiers as high speed memory in a memory system 失效
标题翻译：锁存读出放大器作为存储器系统中的高速存储器
公开(公告)号：US20040260983A1
公开(公告)日：2004-12-23
申请号：US10800382
申请日：2004-03-11
申请人： Monolithic System Technology, Inc.
发明人： Wing Yu Leung , Fu-Chieh Hsu
IPC分类号： H02H003/05
CPC分类号： H04L25/0272 , G06F11/006 , G06F11/10 , G06F11/1032 , G06F11/2007 , G06F12/0661 , G06F13/4077 , G11C5/04 , G11C29/006 , G11C29/08 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/81 , G11C29/832 , G11C29/88 , G11C2029/0401 , G11C2029/0411 , G11C2029/4402 , H01L22/22 , H01L27/0203 , H04L5/1461 , H04L25/026 , H04L25/028 , H04L25/029 , H04L25/0292 , Y10S257/907
摘要： A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (5 12 K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) Use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) Use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; and 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.
摘要翻译：容错的高速晶片秤系统包括多个功能模块，对互连网络中的缺陷容错的并行分层总线以及一个或多个总线主机。该总线包括分段成多个总线线路，并通过互连网络中的可编程总线开关和总线收发器或中继器连接在一起。通过：1）使用小块大小（5 12 K位）作为内存模块; 2）使用可编程标识寄存器来促进动态地址映射并相对容易地整合全局冗余; 3）使用网格结构为总线提供互联网络的全局冗余; 4）使用由13条信号线组成的较窄的总线，使总线占用的总面积较小; 5）使用由可编程开关和可编程总线收发器连接的分段总线，以便于轻松隔离总线缺陷; 6）使用专用电路进行总线收发器和异步握手，方便动态总线配置; 7）使用可编程控制寄存器，方便运行时总线重新配置; 8）使用备用总线为总线提供局部冗余; 和9）在内存模块中使用备用行和列提供局部冗余，获得分层总线中的高缺陷容限。

3. 发明申请

US20040061148A1 One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region 失效
标题翻译：具有电隔离电荷存储区域的大容量CMOS工艺中的单晶体管浮体DRAM单元
公开(公告)号：US20040061148A1
公开(公告)日：2004-04-01
申请号：US10676695
申请日：2003-09-30
申请人： Monolithic System Technology, Inc.
发明人： Fu-Chieh Hsu
IPC分类号： H01L027/148 , H01L029/768
CPC分类号： H01L27/108 , H01L27/0214 , H01L27/10802 , H01L27/10873 , H01L29/7841
摘要： A one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell is provided that includes a field-effect transistor fabricated using a process compatible with a standard CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region. A buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region. A bias voltage can be applied to the buried region, thereby controlling leakage currents in the 1T/FB DRAM cell.
摘要翻译：提供了一个单晶体管浮体（1T / FB）动态随机存取存储器（DRAM）单元，其包括使用与标准CMOS工艺兼容的工艺制造的场效应晶体管。场效应晶体管包括位于源极区域和漏极区域之间的第一导电类型的源极区域和漏极区域以及与第一导电类型相反的第二导电类型的浮动体区域。第一导电类型的掩埋区域位于源极区域，漏极区域和浮体区域的下方。掩埋区域有助于形成耗尽区，其位于掩埋区域与源极区域，漏极区域和浮体区域之间。浮体区由此被耗尽区隔离。可以将偏置电压施加到掩埋区域，从而控制1T / FB DRAM单元中的漏电流。

4. 发明申请

US20030151072A1 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same 有权
公开(公告)号：US20030151072A1
公开(公告)日：2003-08-14
申请号：US10374956
申请日：2003-02-25
申请人： Monolithic System Technology, Inc.
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L031/0328
CPC分类号： H01L27/1085 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

5. 发明申请

US20030151071A1 DRAM cell having a capacitor structure fabricated partially in a cavity and method for operating same 有权
公开(公告)号：US20030151071A1
公开(公告)日：2003-08-14
申请号：US10374917
申请日：2003-02-25
申请人： Monolithic System Technology, Inc.
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L031/0328
CPC分类号： H01L27/1085 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

6. 发明申请

US20020008271A1 Non-volatile memory system 有权
标题翻译：非易失性存储器系统
公开(公告)号：US20020008271A1
公开(公告)日：2002-01-24
申请号：US09948163
申请日：2001-09-06
申请人： Monolithic System Technology, Inc.
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： H01L029/76 , H01L027/108
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory (NVM) system includes a NVM cell having: a semiconductor region having a first conductivity type; a gate dielectric layer located over the semiconductor region; a gate electrode located over the gate dielectric layer; a source region and a drain region of a second conductivity type, opposite the first conductivity type, located in the semiconductor region and aligned with the gate electrode; a crown electrode having a base that contacts the gate electrode and walls that extend vertically from the base region, away from the gate electrode; a dielectric layer located over the crown electrode, wherein the dielectric layer extends over at least interior surfaces of the walls; and a plate electrode located over the dielectric layer, wherein the plate electrode extends over at least interior surfaces of the walls.
摘要翻译：非易失性存储器（NVM）系统包括具有：具有第一导电类型的半导体区域的NVM单元; 位于所述半导体区域上方的栅介质层; 位于所述栅极电介质层上方的栅电极; 与第一导电类型相反的第二导电类型的源极区域和漏极区域，位于半导体区域中并与栅电极对准; 冠电极，其具有与栅电极接触的基极和从基极区域垂直延伸的壁，远离栅电极; 位于所述冠状电极之上的电介质层，其中所述电介质层至少在所述壁的内表面上延伸; 以及位于所述电介质层上方的平板电极，其中所述平板电极至少在所述壁的内表面上延伸。

7. 发明申请

US20040104407A1 Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region 失效
公开(公告)号：US20040104407A1
公开(公告)日：2004-06-03
申请号：US10705112
申请日：2003-11-10
申请人： Monolithic System Technology, Inc.
发明人： Fu-Chieh Hsu
IPC分类号： H01L031/109
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/10891 , H01L29/7841
摘要： A vertical one-transistor, floating-body DRAM cell is fabricated by forming an isolation region in a semiconductor substrate, thereby defining a semiconductor island in the substrate. A buried source region is formed in the substrate, wherein the top/bottom interfaces of the buried source region are located above/below the bottom of the isolation region, respectively. A recessed region is etched into the isolation region, thereby exposing sidewalls of the semiconductor island, which extend below the top interface of the buried source region. A gate dielectric is formed over the exposed sidewalls, and a gate electrode is formed in the recessed region, over the gate dielectric. A drain region is formed at the upper surface of the semiconductor island region, thereby forming a floating body region between the drain region and the buried source region. Dielectric spacers are formed adjacent to the gate electrode, thereby covering exposed edges of the gate dielectric.

8. 发明申请

US20030147277A1 Non-volatile memory cell fabricated with slight modification to a conventional logic process and methods of operating same 失效
标题翻译：用常规逻辑过程轻微修改制造的非易失性存储器单元及其操作方法
公开(公告)号：US20030147277A1
公开(公告)日：2003-08-07
申请号：US10355477
申请日：2003-01-31
申请人： Monolithic System Technology, Inc.
发明人： Fu-Chieh Hsu
IPC分类号： G11C016/04
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell is fabricated using a conventional logic process, with minor modifications. The cell is fabricated by forming a shallow trench isolation (STI) region in a well region of a semiconductor substrate. A recessed region is formed in the STI region, wherein the recessed region extends into the STI region and exposes a sidewall region in the well region. A capacitor region is formed in the sidewall region. A dielectric layer is formed over the well region, including the sidewall region. A gate electrode is then formed over the dielectric layer, wherein a portion of the gate electrode extends into the recessed region. An access transistor of the cell is then formed in a self-aligned manner with respect to the gate electrode. A capacitor structure is formed by the gate electrode (in the recessed region), the dielectric layer on the sidewall region, and the capacitor region.
摘要翻译：使用常规逻辑过程制造非易失性存储器单元，并进行微小修改。通过在半导体衬底的阱区域中形成浅沟槽隔离（STI）区域来制造电池。在STI区域中形成凹陷区域，其中凹入区域延伸到STI区域中并且暴露出阱区域中的侧壁区域。在侧壁区域中形成电容器区域。在阱区域上形成介电层，包括侧壁区域。然后在电介质层上形成栅电极，其中栅电极的一部分延伸到凹陷区域中。然后以相对于栅电极的自对准方式形成电池的存取晶体管。电容器结构由栅电极（凹陷区域），侧壁区域的电介质层和电容器区域形成。

9. 发明申请

US20020154541A1 Non-volatile memory embedded in a conventional logic process 失效
标题翻译：嵌入在常规逻辑过程中的非易失性存储器
公开(公告)号：US20020154541A1
公开(公告)日：2002-10-24
申请号：US10165589
申请日：2002-06-07
申请人： Monolithic System Technology, Inc.
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G11C011/34 , G06F013/00
CPC分类号： H01L27/11521 , G11C7/20 , G11C16/0416 , G11C2216/10 , H01L21/28273 , H01L27/11558 , H01L29/66825
摘要： A non-volatile memory cell fabricated using a conventional logic process. As used herein, a conventional logic process is defined as a semiconductor process that implements single-well or twin-well technology and uses only one layer of polysilicon. The non-volatile memory cell uses a thin gate oxide (i.e., 1.5 nm to 6 nm) commonly available in a conventional logic process. This non-volatile memory cell can be programmed and erased using relatively low voltages. As a result, the voltages required to program and erase can be provided by transistors readily available in a conventional logic process. The program and erase voltages are precisely controlled to avoid the need for a triple-well process. In one embodiment, the non-volatile memory cells are configured to form a non-volatile memory block that is used in a system-on-a-chip. In this embodiment, the contents of the non-volatile memory cells are read out and stored (with or without data decompression operations) into on-chip or off-chip volatile memory. The data contents of the non-volatile memory cells are then refreshed (through charge injection and removal) with optimum signal condition. The non-volatile memory cells then remain in an idle or standby mode substantially without a significant external electric field. If a reprogramming operation or a refresh operation is required, then the non-volatile memory cells are reprogrammed or refreshed as required and then returned to the idle or standby mode. As a result, the storage characteristics of the thin oxide non-volatile memory cells are improved.
摘要翻译：使用常规逻辑过程制造的非易失性存储单元。如本文所使用的，常规逻辑过程被定义为实现单井或双井技术并且仅使用一层多晶硅的半导体工艺。非易失性存储单元使用通常在常规逻辑处理中可获得的薄栅极氧化物（即，1.5nm至6nm）。该非易失性存储单元可以使用相对较低的电压进行编程和擦除。结果，编程和擦除所需的电压可以由常规逻辑处理器中容易获得的晶体管提供。精确地控制编程和擦除电压，以避免需要三阱工艺。在一个实施例中，非易失性存储器单元被配置为形成在片上系统中使用的非易失性存储器块。在本实施例中，将非易失性存储单元的内容读出并存储（具有或不具有数据解压缩操作）到片上或片外易失性存储器中。然后通过最佳信号条件刷新非易失性存储单元的数据内容（通过电荷注入和去除）。然后，非易失性存储器单元基本上没有显着的外部电场而保持在空闲或待机模式。如果需要重新编程操作或刷新操作，则根据需要重新编程或刷新非易失性存储单元，然后返回到空闲或待机模式。结果，提高了薄氧化物非易失性存储单元的存储特性。

10. 发明申请

US20030001181A1 Method of fabricating a DRAM cell having a thin dielectric access transistor and a thick dielectric storage capacitor 有权
标题翻译：制造具有薄介质存取晶体管和厚介电存储电容器的DRAM单元的方法
公开(公告)号：US20030001181A1
公开(公告)日：2003-01-02
申请号：US10231800
申请日：2002-08-28
申请人： Monolithic System Technology, Inc.
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L029/94
CPC分类号： G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L21/76895 , H01L27/0214 , H01L27/10835 , H01L27/1085 , H01L27/10852 , H01L27/10873 , H01L28/86 , H01L28/91
摘要： A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow Pnull and/or Nnull regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow Pnull and Nnull regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.
摘要翻译：一种包括具有存取晶体管和存储电容器的DRAM单元的存储器系统。存储电容器通过形成多晶硅冠电极，覆盖多晶硅冠的电介质层和覆盖在电介质层上的多晶硅板电极来制造。在形成存储电容器期间执行第一组热循环以形成和退火电容器结构的元件。随后，通过离子注入形成浅的P +和/或N +区，形成金属硅化物。结果，形成电容器结构所需的相对高的第一组热循环不会对浅的P +和N +区域或金属硅化物产生不利影响。在浅区域和金属硅化物的形成期间执行第二组热循环，其与第一组热循环相当或者小于第一组热循环。

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