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1. 发明授权

US5753145A Polarizer films with high thermal and hygroscopic stability 失效
标题翻译：具有高热吸湿稳定性的偏光膜
公开(公告)号：US5753145A
公开(公告)日：1998-05-19
申请号：US458388
申请日：1995-06-02
申请人： Chia-Chi Teng , Hyun Nam Yoon , Mohammad Mortazavi
发明人： Chia-Chi Teng , Hyun Nam Yoon , Mohammad Mortazavi
IPC分类号： C08J5/18 , C08K5/00 , C08L67/03 , C08L69/00 , C08L71/12 , C08L73/00 , C08L75/04 , C08L77/10 , C08L77/12 , C08L101/12 , G02B5/30 , F21V9/14 , C09K19/00
CPC分类号： G02B5/3033
摘要： This invention provides novel liquid crystalline polymers which, when blended with a suitable dye at a suitable high temperature and extruded, yields polarizer films with superior thermal and hygroscopic stability and polarizing efficiency. The invention further provides a process to prepare such polarizer films.
摘要翻译：本发明提供了新颖的液晶聚合物，当在合适的高温下与合适的染料混合并挤出时，产生具有优异的热吸湿稳定性和极化效率的偏振片。本发明还提供了制备这种偏光膜的方法。

2. 发明授权

US5667719A High extinction polarizer films comprising liquid crystal polymeric moieties 失效
标题翻译：包含液晶聚合物部分的高消光偏振膜
公开(公告)号：US5667719A
公开(公告)日：1997-09-16
申请号：US459581
申请日：1995-06-02
申请人： Mohammad Mortazavi , Hyun Nam Yoon , Chia-Chi Teng
发明人： Mohammad Mortazavi , Hyun Nam Yoon , Chia-Chi Teng
IPC分类号： C08J5/18 , C08K5/00 , C08L67/03 , C08L69/00 , C08L71/12 , C08L73/00 , C08L75/04 , C08L77/10 , C08L77/12 , C08L101/12 , C09K19/50 , G02B5/30 , C09K19/52 , C09K19/56 , F21V9/14 , G02F1/1335
CPC分类号： C09K19/50 , G02B5/3016
摘要： This invention provides all organic high extinction polarizers based on blends of novel liquid crystalline polymers and suitable dichroic dyes. The invention further provides a process to prepare such polarizer films.
摘要翻译：本发明提供了基于新型液晶聚合物和合适的二色性染料的共混物的所有有机高消光偏振器。本发明还提供了制备这种偏光膜的方法。

3. 发明授权

US5672296A Polarizer films comprising wholly aromatic liquid crystalline polymers and dichroic dyes 失效
标题翻译：包含全芳族液晶聚合物和二色性染料的偏振片
公开(公告)号：US5672296A
公开(公告)日：1997-09-30
申请号：US460288
申请日：1995-06-02
申请人： Sunny S. Shen , Hyun Nam Yoon , Mohammad Mortazavi
发明人： Sunny S. Shen , Hyun Nam Yoon , Mohammad Mortazavi
IPC分类号： C08J5/18 , C09K19/38 , C09K19/60 , G02B5/30 , C09K19/52 , C09K19/56 , F21V9/14 , G02F1/1335
CPC分类号： C09K19/60 , G02B5/3016 , Y10T428/1041
摘要： This invention provides novel liquid crystalline polymers which, when mixed with a suitable dye and extruded, yields polarizer films with superior polarizing efficiency, transmittance, dichroic ratio, and thermal and humidity stability. The invention further provides a process to prepare such polymers and polarizer films therefrom.
摘要翻译：本发明提供新颖的液晶聚合物，当与合适的染料混合并挤出时，产生具有优异的偏振效率，透射率，二色性比和热和湿稳定性的偏振片。本发明还提供从其制备这种聚合物和偏振片的方法。

4. 发明授权

US07647220B2 Transistor-level timing analysis using embedded simulation 失效
标题翻译：使用嵌入式仿真的晶体管级定时分析
公开(公告)号：US07647220B2
公开(公告)日：2010-01-12
申请号：US10042512
申请日：2001-10-18
申请人： Pawan Kulshreshtha , Robert J. Palermo , Mohammad Mortazavi , Cyrus Bamji , Hakan Yalcin
发明人： Pawan Kulshreshtha , Robert J. Palermo , Mohammad Mortazavi , Cyrus Bamji , Hakan Yalcin
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.
摘要翻译：公开了一种用于晶体管级静态时序分析的高精度方法。精确的静态定时验证要求精确计算各个门和互连延迟。在亚微米级，使用延迟模型计算门和互连延迟可能导致精度降低。相反，所提出的方法通过使用嵌入式电路模拟器的数值积分来计算延迟。考虑到短路电流，并仔细选择导致每个门极差延迟严格上限的一组条件。自动识别电路中相似的重复晶体管配置，并且一种新颖的基于插值的缓存方案可以从相似门的延迟中快速计算门延迟。与商用高速晶体管级电路仿真器紧密的目标代码级集成可以有效地调用仿真。

5. 发明授权

US06877143B1 System and method for timing abstraction of digital logic circuits 有权
标题翻译：数字逻辑电路定时抽象的系统和方法
公开(公告)号：US06877143B1
公开(公告)日：2005-04-05
申请号：US10226632
申请日：2002-08-23
申请人： Robert J Palermo , Karem A. Sakallah , Shekaripuram V. Venkatesh , Mohammad Mortazavi
发明人： Robert J Palermo , Karem A. Sakallah , Shekaripuram V. Venkatesh , Mohammad Mortazavi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.
摘要翻译：计算机实现的方法提取数字逻辑电路内部的锁存器的时序约束，从而产生时钟表征模型。接收包含在数字逻辑电路中的锁存器和组合逻辑电路的定时信息（例如传播延迟，设置和保持要求），以及用于为电路计时的一类时钟方案的描述。为时钟方案类选择时钟参数。数字逻辑电路的内部时序约束表示为时钟参数的函数的时序约束表达式。这些表达式被组合以定义以时钟参数表示的可行时钟操作的区域。

6. 发明授权

US06442739B1 System and method for timing abstraction of digital logic circuits 有权
标题翻译：数字逻辑电路定时抽象的系统和方法
公开(公告)号：US06442739B1
公开(公告)日：2002-08-27
申请号：US09215633
申请日：1998-12-17
申请人： Robert J. Palermo , Karem A. Sakallah , Shekaripuram V. Venkatesh , Mohammad Mortazavi
发明人： Robert J. Palermo , Karem A. Sakallah , Shekaripuram V. Venkatesh , Mohammad Mortazavi
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.
摘要翻译：计算机实现的方法提取数字逻辑电路内部的锁存器的时序约束，从而产生时钟表征模型。接收包含在数字逻辑电路中的锁存器和组合逻辑电路的定时信息（例如传播延迟，设置和保持要求），以及用于为电路计时的一类时钟方案的描述。为时钟方案类选择时钟参数。数字逻辑电路的内部时序约束表示为时钟参数的函数的时序约束表达式。这些表达式被组合以定义以时钟参数表示的可行时钟操作的区域。

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