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1. 发明授权

US06282554B1 Method and apparatus for floating point operations and format conversion operations 失效
标题翻译：用于浮点运算和格式转换操作的方法和装置
公开(公告)号：US06282554B1
公开(公告)日：2001-08-28
申请号：US09071466
申请日：1998-04-30
申请人： Mohammad A. Abdallah , Prasad Modali
发明人： Mohammad A. Abdallah , Prasad Modali
IPC分类号： G06F700
CPC分类号： H03M7/24
摘要： A floating point arithmetic apparatus for converting numbers between an integer format and a floating point format, wherein a conversion operation requires a greater data path width than a conversion operation. The apparatus comprises right shift circuitry that receives a number in the floating point format, wherein the right shift circuitry includes additional register positions to accommodate a shift beyond a data path width required by an arithmetic operation.
摘要翻译：一种用于在整数格式和浮点格式之间转换数字的浮点算术装置，其中转换操作需要比转换操作更大的数据路径宽度。该装置包括接收浮点格式的数字的右移位电路，其中右移电路包括附加的寄存器位置，以适应超出算术运算所需的数据路径宽度的移位。

2. 发明授权

US08327115B2 Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode 有权
标题翻译：执行单元的多个矩阵，用于以超级或单独模式在单个时钟周期内处理行相关指令的矩阵
公开(公告)号：US08327115B2
公开(公告)日：2012-12-04
申请号：US12296919
申请日：2007-04-12
申请人： Mohammad A. Abdallah
发明人： Mohammad A. Abdallah
IPC分类号： G06F15/76
CPC分类号： G06F15/8007 , G06F7/483 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30109 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F15/80
摘要： A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.
摘要翻译：执行块的矩阵形成一组行和列。这些行支持并行执行指令，列支持依赖指令的执行。执行块的矩阵处理指定并行和从属指令的单个指令块。

3. 发明授权

US6122725A Executing partial-width packed data instructions 失效
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US6122725A
公开(公告)日：2000-09-19
申请号：US53002
申请日：1998-03-31
申请人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
发明人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30181 , G06F9/30185 , G06F9/30196
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.
摘要翻译：提供了一种用于执行标量打包数据指令的方法和装置。根据本发明的一个方面，处理器包括多个寄存器，耦合到多个寄存器的寄存器重命名单元和耦合到寄存器重命名单元的解码器。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器被配置为对构造寄存器文件中的每个指定一个或多个寄存器的第一和第二组指令（例如，一组全宽度压缩数据指令和一组部分宽度压缩数据指令）进行解码。第一组指令中的每个指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相反，第二组指令中的每个指令指定仅对存储在一个或多个指定寄存器中的数据元素的子集执行的操作。

4. 发明授权

US07516307B2 Processor for computing a packed sum of absolute differences and packed multiply-add 有权
标题翻译：用于计算绝对差异和压缩乘积的压缩和的处理器
公开(公告)号：US07516307B2
公开(公告)日：2009-04-07
申请号：US10005728
申请日：2001-11-06
申请人： Mohammad A. Abdallah , Vladimir Pentkovski
发明人： Mohammad A. Abdallah , Vladimir Pentkovski
IPC分类号： G06F9/22 , G06F9/302
CPC分类号： G06F7/544 , G06F7/5332 , G06F7/5443 , G06F9/30021 , G06F9/30036 , G06F17/10 , G06F2207/3828 , G06F2207/5442
摘要： A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to one embodiment, a processor includes a decode unit to decode a packed sum of absolute differences (PSAD) instruction having an opcode format to identify a set of packed data operands. The decode unit initiates a sequence of operations on the set of packed data operands in response to decoding the PSAD instruction. An execution unit performs a first operation of the sequence of operations initiated by the decode logic, and a bus provides the execution unit with the set of packed data operands as identified in accordance with the opcode format.
摘要翻译：公开了一种从压缩数据计算多个绝对差异并将多个绝对差中的每一个相加在一起以产生结果的方法和装置。根据一个实施例，处理器包括解码单元，用于解码具有操作码格式的绝对差（PSAD）指令的压缩和，以标识一组压缩数据操作数。响应于解码PSAD指令，解码单元启动对该组打包数据操作数的操作序列。执行单元执行由解码逻辑发起的操作序列的第一操作，并且总线向执行单元提供根据操作码格式识别的打包数据操作数集合。

5. 发明授权

US06498605B2 Pixel span depth buffer 失效
标题翻译：像素跨度深度缓冲区
公开(公告)号：US06498605B2
公开(公告)日：2002-12-24
申请号：US09442663
申请日：1999-11-18
申请人： Mohammad A. Abdallah
发明人： Mohammad A. Abdallah
IPC分类号： G06T1540
CPC分类号： G06T15/40
摘要： An efficient way to determine which objects in a 3D image are to be displayed and which are not because they are obscured by other displayed objects. Displayable elements are assigned depth values defining their relative perceived nearness to the viewer of the image. A comparison of depth values determines which elements are to be displayed and which are not to be displayed because they are obscured by displayed elements. Rather than comparing the depth value of every pixel in a displayable object to determine whether it is to be displayed, the invention compares groups of pixels defined by spans. Minimum and maximum depth values are determined for each span so that depth variations within a span can be accommodated. Masks are used when only partial spans are to be considered because some pixels in a span are outside the pixel boundaries being considered in a particular comparison.
摘要翻译：确定要显示3D图像中哪些对象的有效方法，哪些不是因为它们被其他显示对象遮挡。可显示元素被分配深度值，定义其与图像的观看者的相对感知的接近度。深度值的比较确定要显示哪些元素以及不显示哪些元素，因为它们被显示的元素遮蔽。不是比较可显示对象中的每个像素的深度值来确定是否要显示它，而是比较由跨度定义的像素组。对于每个跨度确定最小和最大深度值，以便可以适应跨度内的深度变化。当仅考虑部分跨度时使用掩模，因为跨度中的某些像素在特定比较中被考虑的像素边界之外。

6. 发明授权

US06377970B1 Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry 失效
标题翻译：用于使用SIMD乘法电路计算压缩数据元素之和的方法和装置
公开(公告)号：US06377970B1
公开(公告)日：2002-04-23
申请号：US09052904
申请日：1998-03-31
申请人： Mohammad A. Abdallah , Vladimir Pentkovski
发明人： Mohammad A. Abdallah , Vladimir Pentkovski
IPC分类号： G06F752
CPC分类号： G06F7/544 , G06F7/5332 , G06F7/5443 , G06F9/30021 , G06F9/30036 , G06F17/10 , G06F2207/3828 , G06F2207/5442
摘要： A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.
摘要翻译：将打包数据的多个元素中的每一个相加在一起以产生结果的方法和装置。根据一种这样的方法和装置，使用乘法器中的第一组部分乘积选择器来产生部分乘积的第一组部分中的每一个，部分乘积的第一组部分中的每一个为零。使用第二组部分产品选择器将多个元件中的每一个插入到部分产品的第二组部分中的一个中，部分产品的第二组部分中的每一个对齐。将多个元素中的每一个相加在一起以产生包括具有多个元素之和的场的结果。

7. 发明授权

US06918032B1 Hardware predication for conditional instruction path branching 失效
标题翻译：条件指令路径分支的硬件预测
公开(公告)号：US06918032B1
公开(公告)日：2005-07-12
申请号：US09611282
申请日：2000-07-06
申请人： Mohammad A. Abdallah , Khalid D. Al-Dajani
发明人： Mohammad A. Abdallah , Khalid D. Al-Dajani
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/30072 , G06F9/3824 , G06F9/3842 , G06F9/3844
摘要： An instruction associated with a condition is executed. In executing the instruction, a first operation designated by the instruction is performed to produce a first result, and a second operation is performed to produce a second result. Both the first result and the second result are associated with the condition.
摘要翻译：执行与条件相关联的指令。在执行指令时，执行由指令指定的第一操作以产生第一结果，并执行第二操作以产生第二结果。第一个结果和第二个结果都与条件相关联。

8. 发明授权

US06754812B1 Hardware predication for conditional instruction path branching 有权
标题翻译：条件指令路径分支的硬件预测
公开(公告)号：US06754812B1
公开(公告)日：2004-06-22
申请号：US09610895
申请日：2000-07-06
申请人： Mohammad A. Abdallah , Khalid D. Al-Dajani
发明人： Mohammad A. Abdallah , Khalid D. Al-Dajani
IPC分类号： G06F938
CPC分类号： G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/3842 , G06F9/3848
摘要： An instruction associated with a condition is executed when the condition is resolved. In executing the instruction, a first operation designated by the instruction is performed to produce a first result, and a second operation is performed to produce a second result. The first result or the second result is output based on how the condition is resolved.
摘要翻译：当条件解决时，执行与条件相关联的指令。在执行指令时，执行由指令指定的第一操作以产生第一结果，并且执行第二操作以产生第二结果。第一个结果或第二个结果是根据条件如何解决输出的。

9. 发明授权

US06584549B2 System and method for prefetching data into a cache based on miss distance 有权
公开(公告)号：US06584549B2
公开(公告)日：2003-06-24
申请号：US09749936
申请日：2000-12-29
申请人： Mohammad A. Abdallah , Khalid Al-Dajani
发明人： Mohammad A. Abdallah , Khalid Al-Dajani
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F12/0862 , G06F2212/6026
摘要： A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresses of data elements prefetched are determined based on the distance between cache misses recorded in the prefetch table for the instruction.

10. 发明授权

US06269386B1 3X adder 有权
标题翻译： 3X加法器
公开(公告)号：US06269386B1
公开(公告)日：2001-07-31
申请号：US09172933
申请日：1998-10-14
申请人： Scott E. Siers , Mohammad A. Abdallah , Saif M. Alam
发明人： Scott E. Siers , Mohammad A. Abdallah , Saif M. Alam
IPC分类号： G06F750
CPC分类号： G06F7/508 , G06F7/523
摘要： A 3x adder for adding 2a to a, where a is a binary number, the binary numbers 2a and a partitioned so that 2a=(xk . . . x0) and a=(yk . . . y0)where xi and yi have the same size for each i=0, 1, . . . , k, where the 3x adder provides the group generate terms for the sums xi+yi, i=0, 1, . . . , k, according to Boolean expressions, where for any sum xi+yi where xi and yi each have size n1+1, the number of Boolean variables in the product terms in the Boolean expression for the group generate terms of xi+yi do not exceed j+1, where j is the largest integer not exceeding ni/2.
摘要翻译：一个3×加法器，用于将2a加到a，其中a是二进制数，二进制数2a和a被分割，使得2a =（xk。。x0）和a =（yk ... y0），其中xi和yi具有每个i = 0，1，...相同的大小。。。，k，其中3x加法器为和xi + yi，i = 0,1，提供组生成项。。。，k，根据布尔表达式，其中对于任何和xi + yi，其中xi和yi各自具有大小n1 + 1，组中布尔表达式中乘积项中的布尔变量的数量生成xi + yi的项超过j + 1，其中j是不超过ni / 2的最大整数。

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