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1. 发明授权

US5493155A Electric power supply system 失效
标题翻译：电力供应系统
公开(公告)号：US5493155A
公开(公告)日：1996-02-20
申请号：US351048
申请日：1994-11-28
申请人： Mitsuo Okamoto , Hirokazu Kodama , Tsukasa Takebayashi , Kouji Minamino , Yoshikazu Tsuyuguchi , Shigeru Ohmori
发明人： Mitsuo Okamoto , Hirokazu Kodama , Tsukasa Takebayashi , Kouji Minamino , Yoshikazu Tsuyuguchi , Shigeru Ohmori
IPC分类号： H01L31/04 , H02J3/38 , H02J7/34 , H02J7/35 , H02M3/335 , H02J9/00 , H02M1/10
CPC分类号： H02J7/35 , H02M3/33546 , Y02E10/566 , Y10S323/906 , Y10T307/511 , Y10T307/615 , Y10T307/625
摘要： This electric power supply system includes an air conditioner serving as load, a solar photovoltaic cell for supplying power to the air conditioner, and a system power control circuit and further including a commercial power source for use in combination with the solar photovoltaic cell for supplying additional power when insufficient, power is supplied from the solar photovoltaic cell to the air conditioner. In an operation state of the air conditioner, the system power control circuit operates to regulate an operating point of the solar photovoltaic cell and variably regulate the supplied power from the solar photovoltaic cell while comparing required power of the air conditioner with the supplied power from the solar photovoltaic cell.
摘要翻译：该电力供给系统包括作为负载的空调机，向空调机供电的太阳能光伏电池，以及系统功率控制电路，还包括与太阳能光伏电池组合使用的商用电源，用于提供额外的功率不足时，从太阳能光伏电池向空调供电。在空调器的操作状态下，系统功率控制电路用于调节太阳能光伏电池的工作点，并且可以调节来自太阳能光伏电池的供电功率，同时将空调的所需功率与来自太阳能光伏电池。

2. 发明授权

US5181160A Driving circuit for inverter microwave oven 失效
标题翻译：逆变器微波炉驱动电路
公开(公告)号：US5181160A
公开(公告)日：1993-01-19
申请号：US733197
申请日：1991-07-19
申请人： Mitsuo Okamoto , Hirokazu Kodama , Kouji Minamino
发明人： Mitsuo Okamoto , Hirokazu Kodama , Kouji Minamino
IPC分类号： F24C7/02 , H02M3/337 , H02M7/10 , H02M7/12 , H02M7/538 , H05B6/66
CPC分类号： H02M3/3378 , H05B6/66
摘要： A driving circuit for an inverter microwave oven which includes a push-pull voltage type inverter circuit having two sets of switching element groups each provided with more than two switching elements connected in parallel to each other for switching the D.C. current supplied from a D.C. power source, a control device arranged to set a period for simultaneously turning OFF the two sets of switching element groups and to alternately turn ON the switching element groups by the same duty cycle, a step up transformer supplied, at its primary winding having a center tap, with A.C. current from the inverter circuit, and a voltage doubler rectifier circuit connected to a secondary winding of the step-up transformer for supplying electric power to a magnetron through a capacitor. The driving circuit is set so that one half period of a waveform of current flowing through the switching elements becomes equal to the duty cycle by adjusting the leakage inductance of the step-up transformer, the capacitance value of the capacitor and the circuit resistance of the voltage doubler rectifier circuit or the duty cycle of the switching elements.
摘要翻译：一种用于逆变器微波炉的驱动电路，其包括具有两组开关元件组的推挽电压型逆变器电路，每组开关元件组彼此并联连接两个以上的开关元件，用于切换从DC电源提供的DC电流控制装置，其设置为同时关闭所述两组开关元件组的周期并且交替地以相同的占空比将所述开关元件组导通，在其初级绕组上具有中心抽头的升压变压器，来自逆变器电路的交流电流，以及连接到升压变压器的次级绕组的倍压整流电路，用于通过电容器向磁控管提供电力。驱动电路被设定为使得流过开关元件的电流的波形的一半周期通过调节升压变压器的漏电感，电容器的电容值和电路电阻等于占空比电压倍增器整流电路或开关元件的占空比。

3. 发明申请

US20100012951A1 Silicon carbide semiconductor device and method for producing the same 有权
公开(公告)号：US20100012951A1
公开(公告)日：2010-01-21
申请号：US12310992
申请日：2007-09-13
申请人： Tsutomu Yatsuo , Shinsuke Harada , Mitsuo Okamoto , Kenji Fukuda , Makoto Kato
发明人： Tsutomu Yatsuo , Shinsuke Harada , Mitsuo Okamoto , Kenji Fukuda , Makoto Kato
IPC分类号： H01L29/24 , H01L21/336
CPC分类号： H01L29/7802 , H01L21/046 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： In an SiC vertical MOSFET comprising a channel region and an n-type inverted electron guide path formed through ion implantation in a low-concentration p-type deposition film, the width of the channel region may be partly narrowed owing to implantation mask positioning failure, and the withstand voltage of the device may lower, and therefore, the device could hardly satisfy both low on-resistance and high withstand voltage. In the invention, second inverted layers (41, 42) are provided at the same distance on the right and left sides from the inverted layer (40) to be the electron guide path in the device, and the inverted layers are formed through simultaneous ion implantation using the same mask, and accordingly, the length of all the channel regions in the device is made uniform, thereby solving the problem.

4. 发明授权

US5463001A Process for preparing polyolefins 失效
标题翻译：聚烯烃的制备方法
公开(公告)号：US5463001A
公开(公告)日：1995-10-31
申请号：US6695
申请日：1993-01-21
申请人： Akira Sano , Takeichi Shiraishi , Kunihiro Suzuki , Mitsuo Okamoto , Katumi Usui , Hiroyuki Shimizu , Kazuo Matsuura
发明人： Akira Sano , Takeichi Shiraishi , Kunihiro Suzuki , Mitsuo Okamoto , Katumi Usui , Hiroyuki Shimizu , Kazuo Matsuura
IPC分类号： C08F4/658 , C08F4/60 , C08F10/00 , C08F4/656
CPC分类号： C08F10/00
摘要： Polyolefins exhibiting better particle properties are prepared by polymerizing an olefin or olefins in the presence of a catalyst comprising a solid catalyst component and an organometallic compound, said solid catalyst component being prepared by the reaction of the following components [I] and [II]:[I] a reaction product obtained by reacting the following components (1), (2) and (3) with one another in the presence of a compound represented by the general formula ROH wherein R is a hydrocarbon radical having 1 to 20 carbon atoms or an organic residue containing such an element as oxygen, nitrogen, sulfur, or chlorine:(1) a silicon oxide and/or an aluminum oxide;(2) a reaction product obtained by the reaction of a magnesium halide and compound represented by the general formula Me(OR).sub.n X.sub.z-n wherein Me represents an element of Groups I to IV in the Periodic Table, z represents the valence of the element Me, n is 0
摘要翻译：通过在包含固体催化剂组分和有机金属化合物的催化剂存在下聚合烯烃或烯烃来制备表现出更好颗粒性能的聚烯烃，所述固体催化剂组分通过以下组分[I]和[II]的反应制备： [I]通过使下列组分（1），（2）和（3）在通式ROH表示的化合物的存在下反应获得的反应产物，其中R是具有1至20个碳原子的烃基或含有氧，氮，硫或氯等元素的有机残渣：（1）氧化硅和/或氧化铝; （2）通过卤化镁与通式Me（OR）n X z-n表示的化合物反应获得的反应产物，其中Me表示周期表中第I至IV族的元素，z表示元素的化合价 Me，n为0

5. 发明申请

US20090173949A1 SILICON CARBIDE MOS FIELD EFFECT TRANSISTOR WITH BUILT-IN SCHOTTKY DIODE AND METHOD FOR MANUFACTURING SUCH TRANSISTOR 有权
标题翻译：具有内置肖特基二极管的硅碳化物磁场效应晶体管及其制造方法
公开(公告)号：US20090173949A1
公开(公告)日：2009-07-09
申请号：US12281391
申请日：2006-12-27
申请人： Tsutomu Yatsuo , Shinsuke Harada , Kenji Fukuda , Mitsuo Okamoto
发明人： Tsutomu Yatsuo , Shinsuke Harada , Kenji Fukuda , Mitsuo Okamoto
IPC分类号： H01L29/24 , H01L21/336
CPC分类号： H01L21/8213 , H01L27/0727 , H01L29/0619 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7806
摘要： This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.
摘要翻译：本发明具有一个电池，该电池结合了内置的肖特基二极管区域，该区域设置在构成在具有沟道区域和基极区域的低密度p型沉积膜中提供的SiC垂直MOSFET的基本单元的至少一部分中 n型离子注入。该内置的肖特基二极管区域内置有低导通电阻的肖特基二极管，该二极管由设置在高密度栅极层中的第二缺陷盘形成，第二n型基极层穿透低密度p型沉积层形成在其上，到达第二缺陷部分的n型漂移层，并且由于p型沉积层通过从n型杂质离子注入n型杂质而转变为n型，从而形成其自身的形成表面以及以与第二n型基底层的表面暴露部分形成肖特基势垒的方式连接的源电极。

6. 发明授权

US07439635B2 Output suppressing method of a plurality of dispersed power sources and dispersed power source managing system 有权
标题翻译：多个分散电源和分散电源管理系统的输出抑制方法
公开(公告)号：US07439635B2
公开(公告)日：2008-10-21
申请号：US11808437
申请日：2007-06-11
申请人： Hirofumi Nakata , Mitsuo Okamoto
发明人： Hirofumi Nakata , Mitsuo Okamoto
IPC分类号： H02J7/00 , H02J9/00 , H02J3/00 , H02M1/10
CPC分类号： H02J3/32 , H02J3/46 , Y10T307/391 , Y10T307/625 , Y10T307/642
摘要： Regarding output suppression control of a plurality of dispersed power sources linked to a high-voltage-to-low-voltage transformer of a commercial power system, the partiality of the output suppression of a plurality of dispersed power sources is eliminated and, cost increase of the dispersed power sources is prevented. If a voltage at a power receiving point of a dispersed power source 1a exceeds the upper limit of a proper value, then a power conditioner 4 suppresses an output to a power receiving point to store a surplus power into a storage battery 8 and transmit an output suppression start signal to a management unit 9. The management unit 9 transmits an output suppression command signal to the other dispersed power sources 1b through 1e of which the voltage at the power receiving point is not exceeding the upper limit of the proper value to make the other dispersed power sources 1b through 1e to suppress their outputs and store surplus power into storage batteries 8. The plurality of dispersed power sources 1a through 1e can be thus made to impartially suppress the outputs, so that the capacity of the storage batteries 8 can be reduced.
摘要翻译：关于与商用电力系统的高压 - 低压变压器连接的多个分散电源的输出抑制控制，消除了多个分散电源的输出抑制的偏向性，并且成本增加防止分散的电源。如果分散电源1a的受电点的电压超过适当值的上限，则功率调节器4抑制对受电点的输出，以将剩余电力存储到蓄电池8中，并且发送输出抑制开始信号发送到管理单元9。管理单元9将输出抑制命令信号发送到其他分散电源1b至1e，其中电力接收点处的电压不超过适当值的上限，以使其他分散电源1b通过 1 e以抑制其输出并将剩余电力存储到蓄电池8中。因此，可以使多个分散电源1a至1e公正地抑制输出，从而可以减小蓄电池8的容量。

7. 发明申请

US20080203400A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080203400A1
公开(公告)日：2008-08-28
申请号：US12025445
申请日：2008-02-04
申请人： Kenji Fukuda , Junji Senzaki , Shinsuke Harada , Makoto Kato , Tsutomu Yatsuo , Mitsuo Okamoto
发明人： Kenji Fukuda , Junji Senzaki , Shinsuke Harada , Makoto Kato , Tsutomu Yatsuo , Mitsuo Okamoto
IPC分类号： H01L29/161
CPC分类号： H01L29/7802 , H01L21/049 , H01L21/8213 , H01L21/823807 , H01L21/823857 , H01L21/823885 , H01L27/092 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7835
摘要： A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.
摘要翻译：提供半导体器件和使用（000-1）面的碳化硅衬底的器件的制造方法。通过优化栅极氧化后使用的热处理方法来制造具有高阻断电压和高沟道迁移率的SiC半导体器件。制造半导体器件的方法包括以下步骤：在由具有（000-1）面取向的碳化硅形成的半导体区上形成栅极绝缘层，在栅极绝缘层上形成栅电极，在半导体上形成电极区域，清洁半导体区域表面。在800℃至1150℃的温度下，在含有1％或更多的H 2 O（水）蒸气的气氛中形成栅极绝缘层，以降低界面陷阱密度栅极绝缘层和半导体区域之间的界面。

8. 发明申请

US20060057796A1 Silicon carbide semiconductor device and its method of manufacturing method 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US20060057796A1
公开(公告)日：2006-03-16
申请号：US10531582
申请日：2003-10-03
申请人： Shinsuke Harada , Tsutomu Yatsuo , Kenji Fukuda , Mitsuo Okamoto , Kazuhiro Adachi
发明人： Shinsuke Harada , Tsutomu Yatsuo , Kenji Fukuda , Mitsuo Okamoto , Kazuhiro Adachi
IPC分类号： H01L21/8238
CPC分类号： H01L29/66477 , H01L21/02529 , H01L21/0465 , H01L29/1095 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/7802
摘要： A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.
摘要翻译：具有低导通电阻和高阻断电压的碳化硅垂直MOSFET。在第一导电类型的高浓度碳化硅衬底的表面上形成第一导电类型的低浓度碳化硅的第一沉积膜。形成在第一沉积膜上的是第二沉积膜，其包括第二导电类型的高浓度栅极区域，其中第一区域被选择性地去除。在第二沉积膜上形成第三沉积膜，其包括比选择性去除的第一区域宽的第二区域，第一导电类型的高浓度源区域和第二导电类型的低浓度栅极区域。第一导电类型的低浓度基区形成为与第一和第二区域中的第一沉积膜接触。

9. 发明授权

US08003991B2 Silicon carbide MOS field effect transistor with built-in Schottky diode and method for fabrication thereof 有权
标题翻译：具有内置肖特基二极管的碳化硅MOS场效应晶体管及其制造方法
公开(公告)号：US08003991B2
公开(公告)日：2011-08-23
申请号：US12281391
申请日：2006-12-27
申请人： Tsutomu Yatsuo , Shinsuke Harada , Kenji Fukuda , Mitsuo Okamoto
发明人： Tsutomu Yatsuo , Shinsuke Harada , Kenji Fukuda , Mitsuo Okamoto
IPC分类号： H01L29/15
CPC分类号： H01L21/8213 , H01L27/0727 , H01L29/0619 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7806
摘要： This invention has a cell incorporating a built-in Schottky diode region disposed in at least part of an elementary cell that constitutes an SiC vertical MOSFET provided in a low-density p-type deposit film with a channel region and a base region inverted to an n-type by ion implantation. This built-in Schottky diode region has built therein a Schottky diode of low on-resistance that is formed of a second deficient pan disposed in a high-density gate layer, a second n-type base layer penetrating a low-density p-type deposit layer formed thereon, reaching an n-type drift layer of the second deficient part and attaining its own formation in consequence of inversion of the p-type deposit layer into an n-type by the ion implantation of an n-type impurity from the surface, and a source electrode connected in the manner of forming a Schottky barrier to the surface-exposed part of the second n-type base layer.
摘要翻译：本发明具有一个电池，该电池结合了内置的肖特基二极管区域，该区域设置在构成在具有沟道区域和基极区域的低密度p型沉积膜中提供的SiC垂直MOSFET的基本单元的至少一部分中 n型离子注入。该内置的肖特基二极管区域内置有低导通电阻的肖特基二极管，该二极管由设置在高密度栅极层中的第二缺陷盘形成，第二n型基极层穿透低密度p型沉积层形成在其上，到达第二缺陷部分的n型漂移层，并且由于p型沉积层通过从n型杂质离子注入n型杂质而转变为n型，从而形成其自身的形成表面以及以与第二n型基底层的表面暴露部分形成肖特基势垒的方式连接的源电极。

10. 发明授权

US07880173B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07880173B2
公开(公告)日：2011-02-01
申请号：US12025445
申请日：2008-02-04
申请人： Kenji Fukuda , Junji Senzaki , Shinsuke Harada , Makoto Kato , Tsutomu Yatsuo , Mitsuo Okamoto
发明人： Kenji Fukuda , Junji Senzaki , Shinsuke Harada , Makoto Kato , Tsutomu Yatsuo , Mitsuo Okamoto
IPC分类号： H01L29/15
CPC分类号： H01L29/7802 , H01L21/049 , H01L21/8213 , H01L21/823807 , H01L21/823857 , H01L21/823885 , H01L27/092 , H01L29/045 , H01L29/1608 , H01L29/66068 , H01L29/7395 , H01L29/7835
摘要： A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high blocking voltage and high channel mobility is manufactured by optimizing the heat-treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H2O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.
摘要翻译：提供半导体器件和使用（000-1）面的碳化硅衬底的器件的制造方法。通过优化栅极氧化后使用的热处理方法来制造具有高阻断电压和高沟道迁移率的SiC半导体器件。制造半导体器件的方法包括以下步骤：在由具有（000-1）面取向的碳化硅形成的半导体区上形成栅极绝缘层，在栅极绝缘层上形成栅电极，在半导体上形成电极区域，清洁半导体区域表面。栅极绝缘层在800℃至1150℃的温度下在含有1％或更多的H 2 O（水）蒸汽的气氛中形成，以降低栅绝缘层和半导体之间的界面的界面陷阱密度地区。

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