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1. 发明申请

US20070140036A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20070140036A1
公开(公告)日：2007-06-21
申请号：US11678632
申请日：2007-02-26
申请人： Mitsuhiro NOGUCHI , Akira Goda , Hiroyuki Nitta
发明人： Mitsuhiro NOGUCHI , Akira Goda , Hiroyuki Nitta
IPC分类号： G11C7/00
CPC分类号： G06F11/1008 , G06F11/108 , G11C7/22 , G11C16/04 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C29/50004 , G11C29/52 , G11C29/76 , G11C29/82 , G11C29/84 , G11C2029/0409 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.
摘要翻译：半导体存储器件包括：存储单元阵列，具有彼此平行布置的多个数据选择线;多个数据传输线，彼此并联设置，以与数据选择线相交;以及布置的电可重写存储器单元在数据选择线和数据传输线之间的交叉部分; 用于驱动存储单元阵列的数据选择线的数据选择线驱动器; 连接到存储单元阵列的数据传输线的读出放大器电路，用于对数据选择线之一选择的存储器单元执行数据读取; 以及用于对存储单元阵列的数据读取进行定时控制的控制电路，用于根据存储单元阵列的选定数据区输出不同的至少两种类型的定时信号。

2. 发明申请

US20110228583A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110228583A1
公开(公告)日：2011-09-22
申请号：US13035134
申请日：2011-02-25
申请人： Mitsuhiro NOGUCHI , Kenji SAWAMURA , Takeshi KAMIGAICHI , Katsuaki ISOBE
发明人： Mitsuhiro NOGUCHI , Kenji SAWAMURA , Takeshi KAMIGAICHI , Katsuaki ISOBE
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C16/0483 , G11C16/26
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，第一读出放大器电路和第二读出放大器电路。存储单元阵列包括多个第一存储单元单元，多个第二存储单元单元，多个第一互连和多个第二互连。第一读出放大器电路连接到多个第一互连。第二读出放大器电路连接到多个第二互连。互连上表面的高度相等。沿着与第一方向垂直的第二方向的多个第二互连件的每一个的宽度中的至少一个以及沿着垂直于第一方向和第二方向的第三方向的多个第二互连件中的每一个的厚度被设置得较小并且第一读出放大器电路和第二读出放大器电路被设置为跨越存储单元阵列彼此面对。

3. 发明申请

US20090146701A1 SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CHARGE ACCUMULATION LAYER 有权
标题翻译：半导体器件包括具有电荷积累层的存储单元
公开(公告)号：US20090146701A1
公开(公告)日：2009-06-11
申请号：US12326482
申请日：2008-12-02
申请人： Mitsuhiro NOGUCHI , Kenji GOMIKAWA
发明人： Mitsuhiro NOGUCHI , Kenji GOMIKAWA
IPC分类号： H03L7/00 , H01L29/94 , H01L29/792
CPC分类号： G11C16/24 , G11C16/30 , H01L27/0207 , H01L27/0222 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device includes MOS transistors, capacitor elements, a voltage generating circuit, a contact plug, and a memory cell. The MOS transistor and the capacitor element are formed on a first one of the element regions and a second one of the element regions, respectively. In the voltage generating circuit, current paths of the MOS transistors are series-connected and the capacitor elements are connected to the source or drain of the MOS transistors. The contact plug is formed on the source or the drain to connect the MOS transistors or one of the MOS transistors and one of the capacitor elements. A distance between the gate and the contact plug both for a first one of the MOS transistors located in the final stage in the series connection is larger than that for a second one of the MOS transistors located in the initial stage in the series connection.
摘要翻译：半导体器件包括MOS晶体管，电容器元件，电压产生电路，接触插头和存储单元。 MOS晶体管和电容器元件分别形成在第一元件区域和第二元件区域中。在电压产生电路中，MOS晶体管的电流路径串联连接，并且电容器元件连接到MOS晶体管的源极或漏极。接触插塞形成在源极或漏极上，以连接MOS晶体管或MOS晶体管之一以及电容器元件之一。位于串联连接的最后级的MOS晶体管的栅极和接触插塞之间的距离大于串联连接中位于初始阶段的第二个MOS晶体管的距离。

4. 发明申请

US20110298033A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20110298033A1
公开(公告)日：2011-12-08
申请号：US13051355
申请日：2011-03-18
申请人： Junya MATSUNAMI , Mitsuhiro NOGUCHI
发明人： Junya MATSUNAMI , Mitsuhiro NOGUCHI
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/11524 , H01L29/7883
摘要： According to one embodiment, a semiconductor storage device includes a charge storage layer, a control gate. The charge storage layer is formed above a semiconductor substrate with first insulating film disposed therebetween. The control gate is formed above the charge storage layer with second insulating film disposed therebetween. The control gate includes a nickel silicide region. The side surface expands outwardly in at least a partial region thereof, and height of the control gate from a portion at which the side surface thereof starts to expand outwardly to a top of the control gate is greater than maximum width of the control gate in a region above the portion at which the side surface starts to expand outwardly.
摘要翻译：根据一个实施例，半导体存储装置包括电荷存储层，控制栅极。电荷存储层形成在半导体衬底之上，第一绝缘膜位于它们之间。控制栅极形成在电荷存储层上方，其间设置有第二绝缘膜。控制栅极包括硅化镍区域。侧表面在其至少部分区域中向外扩张，并且控制门从其侧表面开始向外膨胀到控制栅极顶部的部分的高度大于控制栅极的最大宽度在侧面开始向外膨胀的部分之上的区域。

5. 发明申请

US20110254097A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WITH TWIN-WELL 失效
标题翻译：非易失性二极管半导体存储器件
公开(公告)号：US20110254097A1
公开(公告)日：2011-10-20
申请号：US13170592
申请日：2011-06-28
申请人： Mitsuhiro NOGUCHI , Minori Kajimoto
发明人： Mitsuhiro NOGUCHI , Minori Kajimoto
IPC分类号： H01L27/088
CPC分类号： H01L27/11546 , H01L27/105 , H01L27/11526
摘要： A nonvolatile semiconductor memory device includes a first well of a first conductivity type, which is formed in a semiconductor substrate of the first conductivity type, a plurality of memory cell transistors that are formed in the first well, a second well of a second conductivity type, which includes a first part that surrounds a side region of the first well and a second part that surrounds a lower region of the first well, and electrically isolates the first well from the semiconductor substrate, and a third well of the second conductivity type, which is formed in the semiconductor substrate. The third well has a less depth than the second part of the second well.
摘要翻译：非易失性半导体存储器件包括形成在第一导电类型的半导体衬底中的第一导电类型的第一阱，形成在第一阱中的多个存储单元晶体管，第二导电类型的第二阱，其包括围绕第一阱的侧部区域的第一部分和围绕第一阱的下部区域的第二部分，并且将第一阱与半导体衬底以及第二导电类型的第三阱电隔离，其形成在半导体衬底中。第三井具有比第二井的第二部分更少的深度。

6. 发明申请

US20100301426A1 DEPLETION MOS TRANSISTOR AND ENHANCEMENT MOS TRANSISTOR 有权
标题翻译：绝缘MOS晶体管和增强MOS晶体管
公开(公告)号：US20100301426A1
公开(公告)日：2010-12-02
申请号：US12788784
申请日：2010-05-27
申请人： Hiroyuki KUTSUKAKE , Kenji GOMIKAWA , Yoshiko KATO , Mitsuhiro NOGUCHI , Masato ENDO
发明人： Hiroyuki KUTSUKAKE , Kenji GOMIKAWA , Yoshiko KATO , Mitsuhiro NOGUCHI , Masato ENDO
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/088 , H01L27/11526 , H01L27/11529 , H01L29/41775 , H01L29/7838
摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
摘要翻译：半导体存储器件包括第一晶体管。第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。沟道区具有第一杂质浓度。源区和漏区具有第二杂质浓度。重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。接触区域具有第四杂质浓度。杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

7. 发明申请

US20090218637A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND DEPLETION-TYPE MOS TRANSISTOR 有权
标题翻译：非易失性半导体存储器件和漏电型MOS晶体管
公开(公告)号：US20090218637A1
公开(公告)日：2009-09-03
申请号：US12359643
申请日：2009-01-26
申请人： Kenji GOMIKAWA , Mitsuhiro NOGUCHI
发明人： Kenji GOMIKAWA , Mitsuhiro NOGUCHI
IPC分类号： H01L29/78
CPC分类号： H01L29/7838 , H01L27/11526 , H01L27/11534
摘要： A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode.A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.
摘要翻译：外围电路至少包括第一晶体管。第一晶体管包括通过栅极绝缘膜形成在半导体层的表面上的栅电极。具有第一杂质浓度的第一导电类型的沟道区形成在栅电极正下方和附近的半导体层的表面上。第一导电类型的源极 - 漏极扩散区形成在半导体层的表面上以夹着栅电极，并且具有大于第一杂质浓度的第二杂质浓度。第一导电类型的重叠区域形成在沟道区域和源极 - 漏极扩散区域重叠的栅电极正下方的半导体层的表面上。重叠区域具有大于第二杂质浓度的第三杂质浓度。

8. 发明申请

US20120236619A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20120236619A1
公开(公告)日：2012-09-20
申请号：US13231510
申请日：2011-09-13
申请人： Hiroyuki KUTSUKAKE , Kikuko SUGIMAE , Mitsuhiro NOGUCHI
发明人： Hiroyuki KUTSUKAKE , Kikuko SUGIMAE , Mitsuhiro NOGUCHI
IPC分类号： G11C5/06
CPC分类号： G11C16/0483 , G11C5/063 , G11C8/14 , H01L27/0207 , H01L27/088 , H01L27/11519 , H01L27/11529
摘要： According to one embodiment, a semiconductor memory device includes a memory array and a peripheral circuit. The memory array has a plurality of memory cells, word lines, and bit lines, in which a first, second, and third blocks are set in the order along the bit line. The peripheral circuit has a transistor group. The transistor group includes a first transfer transistor belonging to the first block, a second transfer transistor belonging to the second block, and a third transfer transistor belonging to the third block. The first, second, and third transfer transistors share the other of a source and a drain of each. With regard to a direction in which either of the source and the drain is connected to the other in each of the first, second, and third transfer transistors, the directions of the adjacent transfer transistors are different from each other by 90° or 180°.
摘要翻译：根据一个实施例，半导体存储器件包括存储器阵列和外围电路。存储器阵列具有多个存储单元，字线和位线，其中按照位线的顺序设置第一，第二和第三块。外围电路具有晶体管组。晶体管组包括属于第一块的第一转移晶体管，属于第二块的第二转移晶体管和属于第三块的第三转移晶体管。第一，第二和第三转移晶体管共享每个的源极和漏极中的另一个。关于源极和漏极中的任一个与第一，第二和第三转移晶体管中的每一个连接到另一个的方向，相邻的转移晶体管的方向彼此相差90°或180° 。

9. 发明申请

US20100038617A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100038617A1
公开(公告)日：2010-02-18
申请号：US12540896
申请日：2009-08-13
申请人： Shingo NAKAJIMA , Eiji ITO , Mitsuhiro NOGUCHI
发明人： Shingo NAKAJIMA , Eiji ITO , Mitsuhiro NOGUCHI
IPC分类号： H01L47/00 , H01L21/36
CPC分类号： H01L27/24
摘要： A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.
摘要翻译：一种具有设置在第一绝缘体上并沿第一方向延伸的第一布线层的半导体存储器件和在第一布线层上以柱形形式设置的非易失性存储单元，元件和可变电阻元件串联连接。可变电阻元件的电阻值根据施加到其上的电压或电流而变化。阻挡层设置在存储单元上并且被配置在面内方向上。导电层设置在阻挡层上并且被配置在面内方向上。第二绝缘体设置在第一绝缘体上并且覆盖存储单元，阻挡层和导电层的侧表面。第二布线层设置在导电层上并沿第二方向延伸。

10. 发明申请

US20110096600A1 SEMICONDUCTOR MEMORY DEVICE REDUCING RESISTANCE FLUCTUATION OF DATA TRANSFER LINE 失效
标题翻译：半导体存储器件降低数据传输线的电阻波动
公开(公告)号：US20110096600A1
公开(公告)日：2011-04-28
申请号：US12877563
申请日：2010-09-08
申请人： Mitsuhiro NOGUCHI
发明人： Mitsuhiro NOGUCHI
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/08 , H01L27/11519 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor memory device includes first and second memory cell blocks and an interconnect rerouting unit provided therebetween. The first memory cell block includes first interconnects and second interconnects provided in each space between the first interconnects. The second memory cell block includes a plurality of third interconnects provided on lines extending from the first interconnects and a plurality of fourth interconnects provided on lines extending from the second interconnects. A width and a thickness of the second and fourth interconnects are smaller than a width and a thickness of the first and second interconnects. Each of the first to fourth interconnects is connected to one end of first to fourth cell units including memory cells. The interconnect rerouting unit connects one of the fourth interconnects to one of the first interconnects and connects one of the third interconnects to the second interconnects.
摘要翻译：根据一个实施例，半导体存储器件包括第一和第二存储单元块以及设置在其间的互连重路由单元。第一存储单元块包括设置在第一互连之间的每个空间中的第一互连和第二互连。第二存储单元块包括设置在从第一互连线延伸的线上的多个第三互连以及设置在从第二互连延伸的线上的多个第四互连。第二和第四互连的宽度和厚度小于第一和第二互连的宽度和厚度。第一至第四互连中的每一个连接到包括存储单元的第一至第四单元单元的一端。互连重路由单元将第四互连中的一个连接到第一互连中的一个，并将第三互连中的一个连接到第二互连。

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