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1. 发明申请

US20110228583A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110228583A1
公开(公告)日：2011-09-22
申请号：US13035134
申请日：2011-02-25
申请人： Mitsuhiro NOGUCHI , Kenji SAWAMURA , Takeshi KAMIGAICHI , Katsuaki ISOBE
发明人： Mitsuhiro NOGUCHI , Kenji SAWAMURA , Takeshi KAMIGAICHI , Katsuaki ISOBE
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C16/0483 , G11C16/26
摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal. At least one of a width of each of the plurality of second interconnects along a second direction perpendicular to the first direction and a thickness of each of the plurality of second interconnects along a third direction perpendicular to the first direction and the second direction is set smaller than each of the plurality of first interconnects, and the first sense amplifier circuit and the second sense amplifier circuit are disposed to face each other across the memory cell array.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元阵列，第一读出放大器电路和第二读出放大器电路。存储单元阵列包括多个第一存储单元单元，多个第二存储单元单元，多个第一互连和多个第二互连。第一读出放大器电路连接到多个第一互连。第二读出放大器电路连接到多个第二互连。互连上表面的高度相等。沿着与第一方向垂直的第二方向的多个第二互连件的每一个的宽度中的至少一个以及沿着垂直于第一方向和第二方向的第三方向的多个第二互连件中的每一个的厚度被设置得较小并且第一读出放大器电路和第二读出放大器电路被设置为跨越存储单元阵列彼此面对。

2. 发明申请

US20110157997A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, METHOD OF READING DATA THEREFROM, AND SEMICONDUCTOR DEVICE 有权
标题翻译：非易失性半导体存储器件，读取数据的方法和半导体器件
公开(公告)号：US20110157997A1
公开(公告)日：2011-06-30
申请号：US12979796
申请日：2010-12-28
申请人： Takeshi KAMIGAICHI , Kenji SAWAMURA
发明人： Takeshi KAMIGAICHI , Kenji SAWAMURA
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5621
摘要： A control circuit is configured to performs, in a write operation to a memory cell and a verify operation for verifying a threshold voltage of the memory cell, a voltage control to provide the memory cell with threshold voltage distributions. The circuit is configured to apply, in a read operation from the memory cell, to a selected memory cell a read voltage between the lower and upper limits of the threshold voltage distributions, and apply to an unselected memory cell a first read-pass voltage higher than the upper limit of a first threshold voltage distribution that is the maximum distribution of the threshold voltage distributions. The circuit is configured to apply, at least during a verify operation in a first write operation conducted before a second write operation that completes writing to the first threshold voltage distribution, a second read-pass voltage lower than the first read-pass voltage to the unselected memory cell, and apply to the semiconductor layer and the source-line a positive voltage.
摘要翻译：控制电路被配置为在对存储器单元的写入操作和用于验证存储器单元的阈值电压的验证操作中执行电压控制，以向存储器单元提供阈值电压分布。该电路被配置为在从存储器单元的读取操作中将阈值电压分布的下限和上限之间的读取电压应用于所选择的存储器单元，并将其应用于未选择的存储器单元的第一读取通过电压超过作为阈值电压分布的最大分布的第一阈值电压分布的上限。该电路被配置为至少在第二写入操作期间在完成对第一阈值电压分布的写入的第二写入操作期间的验证操作期间施加低于第一读通过电压的第二读通过电压未选择的存储单元，并且应用于半导体层和源极线的正电压。

3. 发明申请

US20120198297A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120198297A1
公开(公告)日：2012-08-02
申请号：US13237291
申请日：2011-09-20
申请人： Takeshi KAMIGAICHI , Kenji Sawamura
发明人： Takeshi KAMIGAICHI , Kenji Sawamura
IPC分类号： G11C16/02 , G06F11/07
CPC分类号： G11C11/5628 , G06F1/305 , G11C16/04 , G11C16/12 , G11C16/3404 , G11C29/021 , G11C29/028 , G11C2029/3202
摘要： A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.
摘要翻译：控制电路通过对所选择的字线施加写脉冲电压，对所选字线对1页存储单元执行写操作，然后执行确认数据写入是否完成的验证读操作。当数据写入未完成时，通过一定的升压电压来提高写入脉冲电压的升压动作。位扫描电路根据读出放大器电路中保持的读取数据，确定在同时读取的存储单元中确定达到一定阈值电压的存储单元数是否等于或大于一定数量的验证读取操作。控制电路根据位扫描电路的判定来改变升压电压的量。

4. 发明申请

US20120235222A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120235222A1
公开(公告)日：2012-09-20
申请号：US13237545
申请日：2011-09-20
申请人： Takeshi KAMIGAICHI
发明人： Takeshi KAMIGAICHI
IPC分类号： H01L29/792 , H01L21/76
CPC分类号： H01L27/11524 , H01L21/76229 , H01L27/11519 , H01L29/792
摘要： A device isolation film has a first height in a first area and a second height higher than the first height in a second area. The first area includes a first end of a dummy memory transistor facing a memory string and a part of a device isolation film adjacent thereof. The second area includes a second end of the dummy memory transistor facing a select transistor and a part of the device isolation film adjacent thereof.
摘要翻译：装置隔离膜在第一区域具有第一高度，在第二区域中具有高于第一高度的第二高度。第一区域包括面对存储器串的虚拟存储晶体管的第一端和与其相邻的器件隔离膜的一部分。第二区域包括面对选择晶体管的虚拟存储晶体管的第二端和与其相邻的器件隔离膜的一部分。

5. 发明申请

US20070132007A1 NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME 失效
标题翻译：非易失性半导体存储器及其制造方法
公开(公告)号：US20070132007A1
公开(公告)日：2007-06-14
申请号：US11563069
申请日：2006-11-24
申请人： Takeshi KAMIGAICHI , Yasuhiko Matsunaga
发明人： Takeshi KAMIGAICHI , Yasuhiko Matsunaga
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes active regions . . . AAj-1, AAj, AAj-1, . . . formed in a semiconductor substrate; a plurality of word lines WL0, WL1, . . . in the row direction; memory cell transistors, each including a floating gate provided on the semiconductor substrate via a tunneling insulating film, an inter-gate insulating film disposed on the floating gate, and a control gate disposed on the inter-gate insulating film, disposed on intersections of word lines and active regions; select gate lines SGD in the row direction; bit line contacts CB disposed on the active regions; and a plurality of bit lines in the column direction and connected to the active regions via the bit line contacts; and the bit line contacts are formed by forming an electrode material for the bit line contacts in lines in the row direction and cutting the electrode material for each of the bit lines to avoid contact-failure of bit line contacts CB.
摘要翻译：非易失性半导体存储器包括有源区域。。。 AA j-1，AA，j，j，j-1，...，。。形成在半导体衬底中; 多个字线WL0，WL1，...。。。在行方向存储单元晶体管，每个包括通过隧道绝缘膜设置在半导体衬底上的浮置栅极，设置在浮置栅极上的栅极间绝缘膜，以及设置在栅极间绝缘膜上的控制栅极，设置在字的交叉点上线和活动区域; 在行方向上选择栅极线SGD; 布置在有源区上的位线触点CB; 以及在列方向上的多个位线，并且经由位线触点连接到有源区; 并且通过在行方向上形成用于位线接触的电极材料并切割每个位线的电极材料来形成位线触点，以避免位线触点CB的接触故障。

6. 发明申请

US20110316065A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110316065A1
公开(公告)日：2011-12-29
申请号：US13226224
申请日：2011-09-06
申请人： Takeshi MURATA , Takeshi KAMIGAICHI
发明人： Takeshi MURATA , Takeshi KAMIGAICHI
IPC分类号： H01L29/78
CPC分类号： H01L27/11551 , H01L27/11524 , H01L27/11556 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.
摘要翻译：非易失性半导体存储器件包括具有第一选择晶体管的第一堆叠单元和形成在半导体衬底上的第二选择晶体管和具有第一绝缘层的第二堆叠单元和在第一堆叠单元的上表面上交替堆叠的第一导电层。第二堆叠单元包括与第一绝缘层和第一导电层的侧壁接触形成的第二绝缘层，与用于存储电荷的第二绝缘层接触形成的电荷存储层，形成为接触的第三绝缘层与电荷存储层形成的第一半导体层以及与第三绝缘层接触形成的层叠方向延伸的第一半导体层，一端与第一选择晶体管的一个扩散层连接，另一端与扩散层连接的第二选择晶体管。

7. 发明申请

US20110235413A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件和控制非易失性半导体存储器件的方法
公开(公告)号：US20110235413A1
公开(公告)日：2011-09-29
申请号：US12886847
申请日：2010-09-21
申请人： Takeshi KAMIGAICHI
发明人： Takeshi KAMIGAICHI
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： A control circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention sets the lower limit of an intermediate distribution in a page writing operation such that an amount of shift from a first threshold voltage distribution to a second threshold voltage distribution is substantially equal to an amount of shift from the intermediate distribution to a fourth threshold voltage distribution, and raises the lower limit of the intermediate distribution as the number of times writing has been executed increases. When the threshold voltage distribution of a second memory cell adjoining a reading target first memory cell and subject to data write after the first memory cell is the second or fourth threshold voltage distribution, the control circuit executes control of applying a second reading pass voltage higher than the first reading pass voltage to the second memory cell.
摘要翻译：根据本发明的实施例的非易失性半导体存储器件的控制电路在页写入操作中设定中间分布的下限，使得从第一阈值电压分布到第二阈值电压分布的偏移量基本上等于从中间分布到第四阈值电压分布的偏移量，并且随着写入次数的增加，提高了中间分布的下限。当与第一存储单元相邻的第二存储单元与第一存储单元相邻并经受数据写入的阈值电压分布是第二或第四阈值电压分布时，控制电路执行施加高于第一读取通过电压到第二存储单元。

8. 发明申请

US20090221128A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
标题翻译：具有元件分离区域的非挥发性半导体存储器件
公开(公告)号：US20090221128A1
公开(公告)日：2009-09-03
申请号：US12435842
申请日：2009-05-05
申请人： Michiharu MATSUI , Seiichi MORI , Riichiro SHIROTA , Yuji TAKEUCHI , Takeshi KAMIGAICHI
发明人： Michiharu MATSUI , Seiichi MORI , Riichiro SHIROTA , Yuji TAKEUCHI , Takeshi KAMIGAICHI
IPC分类号： H01L21/28 , H01L21/762
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子经由开口部与第一电极层连接。

9. 发明申请

US20090057814A1 SEMICONDUCTOR MEMORY 有权
标题翻译：半导体存储器
公开(公告)号：US20090057814A1
公开(公告)日：2009-03-05
申请号：US12191592
申请日：2008-08-14
申请人： Tatsuo IZUMI , Takeshi KAMIGAICHI , Shinya TAKAHASHI
发明人： Tatsuo IZUMI , Takeshi KAMIGAICHI , Shinya TAKAHASHI
IPC分类号： H01L27/105
CPC分类号： H01L27/105 , H01L27/0207 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory according to an example of the invention includes active areas, and element isolation areas which isolate the active areas. The active areas and the element isolation areas are arranged alternately in a first direction. An n-th (n is odd number) active area from an endmost portion in the first direction and an (n+1)-th active area are coupled to each other at an endmost portion in a second direction perpendicular to the first direction.
摘要翻译：根据本发明的示例的半导体存储器包括有源区域和隔离有源区域的元件隔离区域。有源区域和元件隔离区域沿第一方向交替布置。从第一方向最端部分的第n（n是奇数）有效区域和第（n + 1）有效区域在垂直于第一方向的第二方向上的最末端处彼此耦合。

10. 发明申请

US20080006869A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20080006869A1
公开(公告)日：2008-01-10
申请号：US11764416
申请日：2007-06-18
申请人： Takeshi KAMIGAICHI , Takeshi Murata , Itaru Kawabata
发明人： Takeshi KAMIGAICHI , Takeshi Murata , Itaru Kawabata
IPC分类号： H01L29/788
CPC分类号： H01L27/11519 , G11C5/06 , G11C5/063 , G11C16/04 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory according to an example of the present application includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
摘要翻译：根据本申请的示例的非易失性半导体存储器包括具有选择栅极晶体管和串联连接的存储单元的单元单元，连接到选择栅极晶体管的选择栅极线和连接到存储单元的字线。字线的一端弯曲到选择栅线侧，并且边缘连接在字线的弯曲点和远端之间。

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